| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/ |
| H A D | mtspmc.c | 93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
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| H A D | mtspmc_private.h | 86 #define PWR_RST_B BIT(0) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/ |
| H A D | mtspmc.c | 98 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
100 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
102 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
103 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
104 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
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| H A D | mtspmc_private.h | 84 #define PWR_RST_B BIT(0) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/ |
| H A D | mtspmc.c | 93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
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| H A D | mtspmc_private.h | 86 #define PWR_RST_B BIT(0) macro
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| /rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/ |
| H A D | mtcmos.c | 18 #define PWR_RST_B BIT(0) macro
103 mmio_clrbits_32(reg, PWR_RST_B); in spm_mtcmos_ctrl()
130 mmio_setbits_32(reg, PWR_RST_B); in spm_mtcmos_ctrl()
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| /rk3399_ARM-atf/plat/mediatek/mt8173/drivers/mtcmos/ |
| H A D | mtcmos.c | 23 PWR_RST_B = 1U << 0 enumerator
144 mmio_clrbits_32(reg_pwr_con, PWR_RST_B); in mtcmos_ctrl_little_off()
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/ |
| H A D | mt_smp.c | 75 mmio_setbits_32(pwr_ctrl->pwpr, PWR_RST_B); in mt_smp_power_core_on()
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| /rk3399_ARM-atf/plat/mediatek/drivers/mcusys/v1/ |
| H A D | mcucfg.h | 87 #define PWR_RST_B BIT(0) macro
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| /rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/ |
| H A D | mcucfg.h | 144 #define PWR_RST_B BIT(0) macro
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