Searched refs:PMU0SGRF_BASE (Results 1 – 5 of 5) sorted by relevance
107 mmio_write_32(PMU0SGRF_BASE + PMU1SGRF_SOC_CON(0), 0xffff1800); in system_reset_init()
26 #define PMU0SGRF_BASE 0xfd580000 macro
29 #define PMU0SGRF_BASE 0x26000000 macro
1008 ddr_data.pmu0sgrf_soc_con1 = mmio_read_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1)); in pmu_sleep_config()1205 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(1), in pmu_sleep_restore()1449 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); in plat_rockchip_pmu_init()1477 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030001); in rockchip_cpu_reset_early()1497 mmio_write_32(PMU0SGRF_BASE + PMU0_SGRF_SOC_CON(2), 0x00030000); in rockchip_cpu_reset_early()
963 mmio_write_32(PMU0SGRF_BASE + PMU0SGRF_SOC_CON(1), 0xffff0000); in rockchip_soc_soft_reset_check_rstout()1045 mmio_write_32(PMU0SGRF_BASE + PMU0SGRF_SOC_CON(2), BITS_WITH_WMASK(1, 0x3, 0)); in plat_rockchip_pmu_init()