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Searched refs:PLL1CPLL_FHCTL0_CFG (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_power.h124 #define PLL1CPLL_FHCTL0_CFG (0x314) macro
H A Dapusys_power.c180 apu_w_are(are_idx++, base_reg + PLL1CPLL_FHCTL0_CFG, in apu_pll_init()