Searched refs:MAIN_PLL0_CFG (Results 1 – 1 of 1) sorted by relevance
38 #define MAIN_PLL0_CFG 0x04060000 macro118 reg_val = mmio_read_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL)); in set_ddr_pll_div()120 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()123 reg_val = mmio_read_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL)); in set_ddr_pll_div()125 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()128 reg_val = mmio_read_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL)); in set_ddr_pll_div()130 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()133 reg_val = mmio_read_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL)); in set_ddr_pll_div()135 mmio_write_32((uintptr_t)(MAIN_PLL0_CFG + MAIN_PLL0_HSDIV2_CTRL), set_val); in set_ddr_pll_div()