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Searched refs:IOU_SLCR_WDT_CLK_SEL (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/include/
H A Dzynqmp_def.h347 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) macro
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.c2229 .control_reg = IOU_SLCR_WDT_CLK_SEL,