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Searched refs:DVFSRC_SW_REQ5 (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_vcorefs.c374 mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL); in spm_vcorefs_args()
395 mmio_write_32(DVFSRC_SW_REQ5, 0U); in spm_vcorefs_args()
398 mmio_write_32(DVFSRC_SW_REQ5, 0U); in spm_vcorefs_args()
H A Dmt_spm_vcorefs.h51 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.c502 mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL); in spm_vcorefs_args()
523 mmio_write_32(DVFSRC_SW_REQ5, 0U); in spm_vcorefs_args()
526 mmio_write_32(DVFSRC_SW_REQ5, 0U); in spm_vcorefs_args()
H A Dmt_spm_vcorefs.h66 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_vcorefs_reg.h22 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x20) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.h77 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_vcorefs_reg.h25 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x20) macro