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Searched refs:DVFSRC_RSRV_4 (Results 1 – 8 of 8) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_vcore_dvfsrc_plat.c195 dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4); in spm_vcorefs_vcore_setting()
260 dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4); in spm_vcorefs_plat_init()
292 if (!(mmio_read_32(DVFSRC_RSRV_4) & V_DRM_ENABLE)) in spm_vcorefs_plat_kick()
H A Dmt_spm_vcorefs_reg.h134 #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x290) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_vcorefs.c343 dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4); in spm_vcorefs_vcore_setting()
386 if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) { in spm_vcorefs_args()
H A Dmt_spm_vcorefs.h67 #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.c472 rsv4 = mmio_read_32(DVFSRC_RSRV_4); in spm_vcorefs_vcore_setting()
514 if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) { in spm_vcorefs_args()
H A Dmt_spm_vcorefs.h189 #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_vcorefs_reg.h116 #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x290) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_vcorefs.h202 #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610) macro