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Searched refs:DVFSRC_DEFAULT_OPP_1 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_vcore_dvfsrc_plat_def.h66 { DVFSRC_DEFAULT_OPP_1, 0x00000000 },
H A Dmt_spm_vcorefs_reg.h91 #define DVFSRC_DEFAULT_OPP_1 (DVFSRC_BASE + 0x22C) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_vcore_dvfsrc_plat_def.h146 { DVFSRC_DEFAULT_OPP_1, 0x00000000 },
H A Dmt_spm_vcorefs_reg.h109 #define DVFSRC_DEFAULT_OPP_1 (DVFSRC_BASE + 0x22C) macro