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Searched refs:DVFSRC_95MD_SCEN_BWU (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_vcore_dvfsrc_plat_def.h58 { DVFSRC_95MD_SCEN_BWU, 0x00000004 },
101 { DVFSRC_95MD_SCEN_BWU, 0x00000002 },
H A Dmt_spm_vcorefs_reg.h110 #define DVFSRC_95MD_SCEN_BWU (DVFSRC_BASE + 0x278) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_vcore_dvfsrc_plat_def.h138 { DVFSRC_95MD_SCEN_BWU, 0x00000009 },
168 { DVFSRC_95MD_SCEN_BWU, 0x00000007 },
181 { DVFSRC_95MD_SCEN_BWU, 0x00000008 },
H A Dmt_spm_vcorefs_reg.h128 #define DVFSRC_95MD_SCEN_BWU (DVFSRC_BASE + 0x278) macro