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Searched refs:DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp2_ddr_regs.h25 #define DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3 BIT(0) macro
/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp2_ddr_helpers.c164 repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) == 0U; in ddr_wait_lp3_mode()
166 repeat_loop = (phyinlpx & DDRPHY_INITENG0_P0_PHYINLPX_PHYINLP3) != 0U; in ddr_wait_lp3_mode()