Searched refs:DDRGRF_BASE (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/rockchip/rk3568/ |
| H A D | rk3568_def.h | 25 #define DDRGRF_BASE 0xfdc40000 macro
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| /rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/ |
| H A D | pmu.c | 651 ddr_data.ddrgrf_con1 = mmio_read_32(DDRGRF_BASE + 0x4); in ddr_sleep_config()
652 mmio_write_32(DDRGRF_BASE + 0x4, BITS_WITH_WMASK(0x0, 0x1f, 0)); in ddr_sleep_config()
661 ddr_data.ddrgrf_con0 = mmio_read_32(DDRGRF_BASE + 0x0); in ddr_sleep_config()
662 mmio_write_32(DDRGRF_BASE + 0x0, BITS_WITH_WMASK(0x0, 0x1, 5)); in ddr_sleep_config()
664 mmio_write_32(DDRGRF_BASE + 0x0, BITS_WITH_WMASK(0x1, 0x1, 4)); in ddr_sleep_config()
680 mmio_write_32(DDRGRF_BASE + 0x0, in ddr_sleep_config_restore()
683 mmio_write_32(DDRGRF_BASE + 0x0, in ddr_sleep_config_restore()
691 mmio_write_32(DDRGRF_BASE + 0x4, in ddr_sleep_config_restore()
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| /rk3399_ARM-atf/plat/rockchip/px30/ |
| H A D | px30_def.h | 121 #define DDRGRF_BASE 0xff630000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/ |
| H A D | pmu.c | 212 grf_ddr_con3 = mmio_read_32(DDRGRF_BASE + GRF_DDR_CON3); in pmu_ddr_suspend_config()
214 mmio_write_32(DDRGRF_BASE + GRF_DDR_CON3, 0x00600020); in pmu_ddr_suspend_config()
356 mmio_write_32(DDRGRF_BASE + GRF_DDR_CON3, grf_ddr_con3 | 0xffff0000); in pmu_reinit()
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