Searched refs:DDRC_STAT (Results 1 – 4 of 4) sorted by relevance
98 val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode in lpddr4_swffc()105 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()131 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()140 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()161 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()224 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()264 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
156 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) == 0x23) { in sw_pstate()214 if ((mmio_read_32(DDRC_STAT(0)) & 0x3) == 0x3) { in ddr4_swffc()228 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) != 0x23) { in ddr4_swffc()
70 while (0x223 != (mmio_read_32(DDRC_STAT(0)) & 0x33f)) { in dram_enter_retention()74 while (0x23 != (mmio_read_32(DDRC_STAT(0)) & 0x3f)) { in dram_enter_retention()210 while (0x1 != (mmio_read_32(DDRC_STAT(0)) & 0x7)) { in dram_exit_retention()
16 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) macro