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Searched refs:CRL_APB_CLK_BASE (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/include/
H A Dzynqmp_def.h67 #define CRL_APB_CLK_BASE U(0xFF5E0020) macro
299 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
300 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
301 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
302 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
303 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
305 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
306 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
307 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
308 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
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