Searched refs:CORES_PM_DISABLE (Results 1 – 9 of 9) sorted by relevance
64 CORES_PM_DISABLE); in cpus_power_domain_on()69 CORES_PM_DISABLE); in cpus_power_domain_on()99 CORES_PM_DISABLE); in cpus_power_domain_off()179 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()188 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
53 #define CORES_PM_DISABLE 0x0 macro
397 WITH_16BITS_WMSK(CORES_PM_DISABLE)); in cpus_power_domain_on()400 WITH_16BITS_WMSK(CORES_PM_DISABLE)); in cpus_power_domain_on()439 WITH_16BITS_WMSK(CORES_PM_DISABLE)); in cpus_power_domain_off()488 WITH_16BITS_WMSK(CORES_PM_DISABLE)); in rockchip_soc_cores_pwr_dm_on_finish()522 WITH_16BITS_WMSK(CORES_PM_DISABLE)); in rockchip_soc_cores_pwr_dm_resume()
67 #define CORES_PM_DISABLE 0x0 macro
54 #define CORES_PM_DISABLE 0x0 macro
507 CORES_PM_DISABLE); in cpus_power_domain_on()544 CORES_PM_DISABLE); in cpus_power_domain_off()709 CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()728 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
84 #define CORES_PM_DISABLE 0x0 macro
134 #define CORES_PM_DISABLE 0x0 macro
163 #define CORES_PM_DISABLE 0x0 macro