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Searched refs:CLK_DIVIDER_POWER_OF_TWO (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.h49 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) macro
H A Dpm_api_clock.c2715 if ((CLK_DIVIDER_POWER_OF_TWO & in pm_api_clock_get_max_divisor()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.h122 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) macro
H A Dclk-stm32-core.c260 if ((flags & CLK_DIVIDER_POWER_OF_TWO) != 0UL) { in _get_div()
H A Dclk-stm32mp13.c810 DIV_CFG(DIV_HSI, RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY),
811 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY),