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Searched refs:CCI_CRU_BASE (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpm_pd_regs.c99 REG_REGION(0x310, 0x310, 4, CCI_CRU_BASE, WMSK_VAL),
100 REG_REGION(0x804, 0x808, 4, CCI_CRU_BASE, WMSK_VAL),
101 REG_REGION(0xa04, 0xa08, 4, CCI_CRU_BASE, WMSK_VAL),
102 REG_REGION(0xc50, 0xc58, 4, CCI_CRU_BASE, WMSK_VAL),
103 REG_REGION(0xd00, 0xd00, 8, CCI_CRU_BASE, 0),
104 REG_REGION(0xd04, 0xd04, 8, CCI_CRU_BASE, WMSK_VAL),
108 REG_REGION(0x040, 0x044, 4, CCI_CRU_BASE, WMSK_VAL),
109 REG_REGION(0x048, 0x048, 4, CCI_CRU_BASE, 0),
110 REG_REGION(0x04c, 0x058, 4, CCI_CRU_BASE, WMSK_VAL),
420 pm_pll_wait_lock(CCI_CRU_BASE + 0x40); in pd_core_restore()
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c499 m = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(16)) >> in rk3576_lpll_get_rate()
502 p = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(17)) >> in rk3576_lpll_get_rate()
505 s = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(17)) >> in rk3576_lpll_get_rate()
508 k = (mmio_read_32(CCI_CRU_BASE + CRU_PLL_CON(18)) >> in rk3576_lpll_get_rate()
736 src = mmio_read_32(CCI_CRU_BASE + CCICRU_CLKSEL_CON(4)) & 0x3000; in clk_scmi_cci_get_rate()
741 div = mmio_read_32(CCI_CRU_BASE + CCICRU_CLKSEL_CON(4)) & 0xf80; in clk_scmi_cci_get_rate()
786 mmio_write_32(CCI_CRU_BASE + CCICRU_CLKSEL_CON(4), in clk_cci_set_rate()
788 mmio_write_32(CCI_CRU_BASE + CCICRU_CLKSEL_CON(4), in clk_cci_set_rate()
790 mmio_write_32(CCI_CRU_BASE + CCICRU_CLKSEL_CON(4), in clk_cci_set_rate()
797 mmio_write_32(CCI_CRU_BASE + CCICRU_CLKSEL_CON(4), in clk_cci_set_rate()
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/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h66 #define CCI_CRU_BASE 0x27248000 macro
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.h99 #define CRU_AUTOCS_CCI_CON(offset) (CCI_CRU_BASE + (offset))