| /optee_os/core/drivers/ |
| H A D | atmel_shdwc_a32.S | 48 ldr r6, [r1, #AT91_SHDW_CR]
49 ldr r6, [r2, #AT91_PMC_MCKR]
62 ldr r6, [r2, #AT91_PMC_MCKR]
63 bic r6, r6, #AT91_PMC_CSS
64 str r6, [r2, #AT91_PMC_MCKR]
68 ldr r6, [r2, #AT91_PMC_SR]
69 tst r6, #AT91_PMC_MCKRDY
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| /optee_os/ldelf/ |
| H A D | start_a32.S | 26 ldr r6, reloc_end_rel
28 add r6, r6, r4
29 cmp r5, r6
47 cmp r5, r6
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| H A D | syscalls_a32.S | 27 mov r6, #0
30 mov r6, #(\num_args - 4)
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| /optee_os/core/arch/arm/crypto/ |
| H A D | aes_modes_armv8a_ce_a32.S | 220 push {r4-r6, lr}
232 pop {r4-r6, pc}
241 push {r4-r6, lr}
275 pop {r4-r6, pc}
284 push {r4-r6, lr}
288 vmov r6, s27 @ keep swabbed ctr in r6
289 rev r6, r6
290 cmn r6, r4 @ 32 bit overflow?
295 add r6, r6, #1
298 rev ip, r6
[all …]
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| /optee_os/core/arch/arm/kernel/ |
| H A D | arch_scall_a32.S | 25 ldr r6, [r8, #THREAD_SCALL_REG_R6]
36 cmp r6, #0
38 sub sp, sp, r6, lsl #2
42 mov r2, r6, lsl #2
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| H A D | thread_a32.S | 143 mrs r6, cpsr /* Save current CPSR */
164 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */
165 msr cpsr, r6 /* Restore mode */
191 mrs r6, cpsr /* Save current CPSR */
214 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */
215 msr cpsr, r6 /* Restore mode */
357 mov sp, r6
941 read_ttbr0_64bit r6, r7 /* These registers must be preseved */
945 add r2, r6, #CORE_MMU_BASE_TABLE_OFFSET
948 write_ttbr0_64bit r6, r3
[all …]
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| H A D | cache_helpers_a32.S | 112 add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions
136 blx r6
147 mov r6, #0
148 write_csselr r6 //select cache level 0 in csselr
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| H A D | entry_a32.S | 42 push { r4-r6, lr }
62 1: pop { r4-r6, pc }
205 mov r6, r2
532 mov r2, r6
818 mov r3, r6 /* std bootarg #2 for register R2 */
1045 mov r6, lr
1085 bx r6
1156 ldm r0, {r0, r6}
1159 mov r6, #0
1170 mov r1, r6
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| H A D | arch_scall.c | 33 .r6 = pushed[7], in save_panic_regs_a32_ta()
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| H A D | stmm_sp.c | 50 #define SVC_REGS_A6(_regs) ((_regs)->r6)
540 spc->regs.r6 = 0; in stmm_enter_invoke_cmd()
622 spc->regs.r6 = regs->r6; in save_sp_ctx()
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| H A D | asm-defines.c | 30 DEFINE(THREAD_SCALL_REG_R6, offsetof(struct thread_scall_regs, r6));
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| H A D | abort.c | 58 state.registers[6] = ai->regs->r6; in __print_stack_unwind()
176 ai->regs->r2, ai->regs->r6, ai->regs->r10, lr); in __print_abort_info()
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| H A D | thread.c | 180 thread->regs.r6 = a6; in init_regs()
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| /optee_os/lib/libutils/isoc/arch/arm/ |
| H A D | setjmp_a32.S | 100 stmia r0!, {r4, r5, r6, r7}
106 mov r6, lr
107 stmia r0!, {r1, r2, r3, r4, r5, r6}
110 ldmia r0!, {r4, r5, r6, r7}
121 ldmia r0!, {r2, r3, r4, r5, r6}
126 mov sp, r6
130 ldmia r0!, {r4, r5, r6, r7}
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| /optee_os/core/arch/arm/sm/ |
| H A D | pm_a32.S | 77 read_ttbr1 r6
87 read_vbar r6
182 write_ttbr1 r6
189 write_vbar r6
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| /optee_os/lib/libutee/arch/arm/ |
| H A D | utee_syscalls_a32.S | 37 mov r6, #0
40 mov r6, #(\num_args - 4)
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| /optee_os/core/arch/arm/include/sm/ |
| H A D | sm.h | 61 uint32_t r6; member
78 uint32_t r6; member
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| /optee_os/core/arch/arm/include/kernel/ |
| H A D | arch_scall.h | 18 *max_args = regs->r6; in scall_get_max_args()
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| H A D | thread_arch.h | 181 uint32_t r6; member
242 uint32_t r6; member
301 uint32_t r6; member
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| /optee_os/core/kernel/ |
| H A D | ldelf_loader.c | 248 arg->arm32.regs[6] = tsd->abort_regs.r6; in ldelf_dump_state()
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| /optee_os/core/drivers/pm/sam/ |
| H A D | pm_suspend.S | 28 tmp3 .req r6
|