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Searched refs:io_caam_write32 (Results 1 – 10 of 10) sorted by relevance

/optee_os/core/drivers/crypto/caam/hal/common/
H A Dhal_rng.c114 io_caam_write32(baseaddr + TRNG_SDCTL, TRNG_SDCTL_ENT_DLY(ent_delay) | in caam_hal_rng_kick()
118 io_caam_write32(baseaddr + TRNG_FRQMIN, ent_delay >> 2); in caam_hal_rng_kick()
121 io_caam_write32(baseaddr + TRNG_FRQMAX, ent_delay << 4); in caam_hal_rng_kick()
123 io_caam_write32(baseaddr + TRNG_RTSCMISC, in caam_hal_rng_kick()
125 io_caam_write32(baseaddr + TRNG_RTPKRRNG, TRNG_RTPKRRNG_PKR_RNG(570)); in caam_hal_rng_kick()
126 io_caam_write32(baseaddr + TRNG_RTPKRMAX, TRNG_RTPKRMAX_PKR_MAX(1600)); in caam_hal_rng_kick()
127 io_caam_write32(baseaddr + TRNG_RTSCML, in caam_hal_rng_kick()
129 io_caam_write32(baseaddr + TRNG_RTSCR1L, in caam_hal_rng_kick()
131 io_caam_write32(baseaddr + TRNG_RTSCR2L, in caam_hal_rng_kick()
133 io_caam_write32(baseaddr + TRNG_RTSCR3L, in caam_hal_rng_kick()
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H A Dhal_jr.c44 io_caam_write32(baseaddr + JRX_JRCR, JRX_JRCR_RESET); in caam_hal_jr_reset()
59 io_caam_write32(baseaddr + JRX_JRCR, JRX_JRCR_RESET); in caam_hal_jr_reset()
80 io_caam_write32(baseaddr + JRX_IRBAR, inrings); in caam_hal_jr_config()
81 io_caam_write32(baseaddr + JRX_IRBAR + 4, inrings >> 32); in caam_hal_jr_config()
83 io_caam_write32(baseaddr + JRX_IRBAR, inrings >> 32); in caam_hal_jr_config()
84 io_caam_write32(baseaddr + JRX_IRBAR + 4, inrings); in caam_hal_jr_config()
86 io_caam_write32(baseaddr + JRX_IRSR, nbjobs); in caam_hal_jr_config()
90 io_caam_write32(baseaddr + JRX_ORBAR, outrings); in caam_hal_jr_config()
91 io_caam_write32(baseaddr + JRX_ORBAR + 4, outrings >> 32); in caam_hal_jr_config()
93 io_caam_write32(baseaddr + JRX_ORBAR, outrings >> 32); in caam_hal_jr_config()
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H A Dhal_sm.c38 io_caam_write32(jr_base + SM_SMCR, SM_SMCR_PAGE(page) | in issue_cmd()
94 io_caam_write32(jr_base + SM_SMAG1(partition), UINT32_MAX); in caam_hal_sm_set_access_all_group()
95 io_caam_write32(jr_base + SM_SMAG2(partition), UINT32_MAX); in caam_hal_sm_set_access_all_group()
104 io_caam_write32(jr_base + SM_SMAG1(partition), grp1); in caam_hal_sm_set_access_group()
105 io_caam_write32(jr_base + SM_SMAG2(partition), grp2); in caam_hal_sm_set_access_group()
110 io_caam_write32(jr_base + SM_SMAPR(partition), in caam_hal_sm_open_access_perm()
117 io_caam_write32(jr_base + SM_SMAPR(partition), in caam_hal_sm_set_access_perm()
H A Dhal_ctrl.c125 io_caam_write32(baseaddr + SCFGR, val); in caam_hal_ctrl_inc_priblob()
224 io_caam_write32(reg, val); in caam_hal_ctrl_fill_mpmr()
237 io_caam_write32(reg, val); in caam_hal_ctrl_fill_mpmr()
244 io_caam_write32(reg, 0x0); in caam_hal_ctrl_fill_mpmr()
250 io_caam_write32(ctrl_addr + SCFGR, in caam_hal_ctrl_fill_mpmr()
/optee_os/core/drivers/crypto/caam/include/
H A Dcaam_io.h18 #define io_caam_write32(a, val) io_write32(a, TEE_U32_TO_BIG_ENDIAN(val)) macro
26 #define io_caam_write32(a, val) io_write32(a, val) macro
/optee_os/core/drivers/crypto/caam/hal/imx_8ulp/
H A Dhal_jr.c76 io_caam_write32(ctrl_base + JRxDID_LS(jr_idx), cfg_ls); in caam_hal_jr_setowner()
77 io_caam_write32(ctrl_base + JRxDID_MS(jr_idx), cfg_ms); in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/hal/imx_8m/
H A Dhal_jr.c75 io_caam_write32(ctrl_base + JRxDID_LS(jr_idx), cfg_ls); in caam_hal_jr_setowner()
76 io_caam_write32(ctrl_base + JRxDID_MS(jr_idx), cfg_ms); in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/hal/imx_6_7/
H A Dhal_jr.c79 io_caam_write32(ctrl_base + JRxMIDR_LS(jr_idx), cfg_ls); in caam_hal_jr_setowner()
80 io_caam_write32(ctrl_base + JRxMIDR_MS(jr_idx), cfg_ms); in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/hal/ls/
H A Dhal_jr.c26 io_caam_write32(ctrl_base + JRxMIDR_MS(jr_idx), val); in caam_hal_jr_setowner()
/optee_os/core/drivers/crypto/caam/
H A Dcaam_pwr.c107 io_caam_write32(elem->baseaddr + reg->offset + in do_restore_regs()