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Searched refs:TRNG_SDCTL_ENT_DLY (Results 1 – 2 of 2) sorted by relevance

/optee_os/core/drivers/crypto/caam/hal/common/registers/
H A Drng_regs.h28 #define TRNG_SDCTL_ENT_DLY(val) SHIFT_U32(((val) & 0xFFFF), 16) macro
/optee_os/core/drivers/crypto/caam/hal/common/
H A Dhal_rng.c114 io_caam_write32(baseaddr + TRNG_SDCTL, TRNG_SDCTL_ENT_DLY(ent_delay) | in caam_hal_rng_kick()