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Searched refs:MCU_MC_CONTROL_0_REG (Results 1 – 2 of 2) sorted by relevance

/optee_os/core/arch/arm/plat-marvell/armada3700/
H A Dhal_sec_perf.c38 #define MCU_MC_CONTROL_0_REG PHY_2_VIR(MCU_BASE + 0x044) macro
130 (x) = io_read32(MCU_MC_CONTROL_0_REG); \
132 io_write32(MCU_MC_CONTROL_0_REG, (x)); \
/optee_os/core/arch/arm/plat-marvell/armada7k8k/
H A Dhal_sec_perf.c37 #define MCU_MC_CONTROL_0_REG PHY_2_VIR(MCU_BASE + 0x044) macro
131 (x) = io_read32(MCU_MC_CONTROL_0_REG); \
133 io_write32(MCU_MC_CONTROL_0_REG, (x)); \