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Searched refs:stream_res (Results 1 – 25 of 27) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_hwss.c123 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz = in dp_enable_link_phy()
127 &pipes[i].stream_res.pix_clk_params, in dp_enable_link_phy()
338 pipes[i].stream_res.stream_enc != NULL && in dp_retrain_link_dp_test()
342 pipes[i].stream_res.stream_enc->funcs->dp_blank( in dp_retrain_link_dp_test()
343 pipes[i].stream_res.stream_enc); in dp_retrain_link_dp_test()
352 if ((&pipes[i])->stream_res.audio && !link->dc->debug.az_endpoint_mute_only) in dp_retrain_link_dp_test()
353 (&pipes[i])->stream_res.audio->funcs->az_disable((&pipes[i])->stream_res.audio); in dp_retrain_link_dp_test()
375 if (pipes[i].stream_res.audio) { in dp_retrain_link_dp_test()
378 pipes[i].stream_res.audio->funcs->az_enable( in dp_retrain_link_dp_test()
379 pipes[i].stream_res.audio); in dp_retrain_link_dp_test()
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H A Ddc.c296 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_adjust_vmin_vmax()
324 if (pipe->stream == stream && pipe->stream_res.stream_enc) { in dc_stream_get_crtc_position()
381 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
415 tg = pipe->stream_res.tg; in dc_stream_get_crc()
434 pipe_ctx->stream_res.opp->dyn_expansion = option; in dc_stream_set_dyn_expansion()
435 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( in dc_stream_set_dyn_expansion()
436 pipe_ctx->stream_res.opp, in dc_stream_set_dyn_expansion()
479 pipes->stream_res.opp->funcs-> in dc_stream_set_dither_option()
480 opp_program_bit_depth_reduction(pipes->stream_res.opp, &params); in dc_stream_set_dither_option()
515 pipes->stream_res.opp->inst); in dc_stream_program_csc_matrix()
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H A Ddc_resource.c1402 split_pipe->stream_res.tg = pool->timing_generators[i]; in acquire_first_split_pipe()
1406 split_pipe->stream_res.opp = pool->opps[i]; in acquire_first_split_pipe()
1476 free_pipe->stream_res.tg = tail_pipe->stream_res.tg; in dc_add_plane_to_context()
1477 free_pipe->stream_res.abm = tail_pipe->stream_res.abm; in dc_add_plane_to_context()
1478 free_pipe->stream_res.opp = tail_pipe->stream_res.opp; in dc_add_plane_to_context()
1479 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; in dc_add_plane_to_context()
1480 free_pipe->stream_res.audio = tail_pipe->stream_res.audio; in dc_add_plane_to_context()
1775 pipe_ctx->stream_res.tg = pool->timing_generators[i]; in acquire_first_free_pipe()
1781 pipe_ctx->stream_res.opp = pool->opps[i]; in acquire_first_free_pipe()
1874 ASSERT(del_pipe->stream_res.stream_enc); in dc_remove_stream_from_ctx()
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H A Ddc_link.c1681 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = in enable_link_dp()
2262 eng_id = pipe_ctx->stream_res.stream_enc->id; in enable_link_hdmi()
2510 abm = pipe_ctx.stream_res.abm; in get_abm_from_stream_res()
2718 pipe_ctx[i].stream_res.tg->inst + 1; in dc_link_setup_psr()
2906 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in dc_link_allocate_mst_payload()
2927 link, pipe_ctx->stream_res.stream_enc, &proposed_table); in dc_link_allocate_mst_payload()
2989 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in deallocate_mst_payload()
3017 link, pipe_ctx->stream_res.stream_enc, &proposed_table); in deallocate_mst_payload()
3099 pipe_ctx->stream_res.stream_enc->id, true); in dc_link_reallocate_mst_payload()
3116 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; in update_psp_stream_config()
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H A Ddc_link_dp.c1631 pipe_ctx->stream_res.stream_enc->id, true); in perform_link_training_with_retries()
3826 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in set_crtc_test_pattern()
3873 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) in set_crtc_test_pattern()
3874 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
3916 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
3937 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) in set_crtc_test_pattern()
3938 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
3951 struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
4046 pipes->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); in dc_link_dp_set_test_pattern()
4149 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { in dc_link_dp_set_test_pattern()
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H A Ddc_debug.c326 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); in context_timing_trace()
337 pipe_ctx->stream_res.tg->inst, in context_timing_trace()
H A Ddc_stream.c535 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter()
594 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_scanoutpos()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c636 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
646 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
647 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
648 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
650 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dce110_update_info_frame()
651 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
652 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
665 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dce110_enable_stream()
672 pipe_ctx->stream_res.stream_enc->id, true); in dce110_enable_stream()
691 if (pipe_ctx->stream_res.audio != NULL) { in dce110_enable_stream()
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H A Ddce110_resource.c902 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
926 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
929 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
1142 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay()
1146 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1157 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay()
1165 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1174 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay()
1175 pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1187 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_acquire_underlay()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_hwseq.c107 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
112 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
134 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
138 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
162 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
163 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
164 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
165 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
169 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
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H A Ddcn20_resource.c1603 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1636 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1640 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
1674 … display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1732 if (pipe_ctx->stream_res.dsc) in dcn20_add_dsc_to_stream_resource()
1735 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); in dcn20_add_dsc_to_stream_resource()
1738 if (!pipe_ctx->stream_res.dsc) { in dcn20_add_dsc_to_stream_resource()
1760 if (pipe_ctx->stream_res.dsc) in remove_dsc_from_stream_resource()
1761 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1882 next_odm_pipe->stream_res.dsc = NULL; in dcn20_split_stream_for_odm()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c96 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
468 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur()
803 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn10_enable_stream_timing()
807 &pipe_ctx->stream_res.pix_clk_params, in dcn10_enable_stream_timing()
813 pipe_ctx->stream_res.tg->funcs->program_timing( in dcn10_enable_stream_timing()
814 pipe_ctx->stream_res.tg, in dcn10_enable_stream_timing()
827 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; in dcn10_enable_stream_timing()
829 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( in dcn10_enable_stream_timing()
830 pipe_ctx->stream_res.opp, in dcn10_enable_stream_timing()
846 if (pipe_ctx->stream_res.tg->funcs->set_blank_color) in dcn10_enable_stream_timing()
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H A Ddcn10_resource.c1073 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1103 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1107 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
1168 idle_pipe->stream_res.tg = head_pipe->stream_res.tg; in dcn10_acquire_idle_pipe_for_layer()
1169 idle_pipe->stream_res.abm = head_pipe->stream_res.abm; in dcn10_acquire_idle_pipe_for_layer()
1170 idle_pipe->stream_res.opp = head_pipe->stream_res.opp; in dcn10_acquire_idle_pipe_for_layer()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_hwseq.c56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
H A Ddmub_psr.c245 if (pipe_ctx->stream_res.opp) in dmub_psr_copy_settings()
246 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; in dmub_psr_copy_settings()
249 if (pipe_ctx->stream_res.tg) in dmub_psr_copy_settings()
250 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
H A Ddce_clk_mgr.c199 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in get_max_pixel_clock_for_all_paths()
200 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in get_max_pixel_clock_for_all_paths()
206 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in get_max_pixel_clock_for_all_paths()
207 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in get_max_pixel_clock_for_all_paths()
520 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_hwseq.c95 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
174 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func()
190 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
644 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) in dcn30_set_avmute()
645 pipe_ctx->stream_res.stream_enc->funcs->set_avmute( in dcn30_set_avmute()
646 pipe_ctx->stream_res.stream_enc, in dcn30_set_avmute()
657 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn30_update_info_frame()
667 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn30_update_info_frame()
668 pipe_ctx->stream_res.stream_enc, in dcn30_update_info_frame()
669 &pipe_ctx->stream_res.encoder_info_frame); in dcn30_update_info_frame()
[all …]
H A Ddcn30_resource.c1869 sec_pipe->stream_res.dsc = NULL; in dcn30_split_stream_for_mpc_or_odm()
1879 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1881 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); in dcn30_split_stream_for_mpc_or_odm()
1882 ASSERT(sec_pipe->stream_res.dsc); in dcn30_split_stream_for_mpc_or_odm()
1883 if (sec_pipe->stream_res.dsc == NULL) in dcn30_split_stream_for_mpc_or_odm()
2064 if (pipe->stream_res.dsc) in dcn30_internal_validate_bw()
2065 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn30_internal_validate_bw()
2067 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn30_internal_validate_bw()
2082 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn30_internal_validate_bw()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_hwseq.c163 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
164 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
181 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_pipe()
182 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_pipe()
201 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_backlight_level()
202 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_backlight_level()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_hw_sequencer.c128 params.inst = pipe_ctx->stream_res.tg->inst; in dce60_enable_fbc()
192 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); in dce60_program_surface_visibility()
200 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in dce60_get_surface_visual_confirm_color()
251 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in dce60_program_scaler()
260 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in dce60_program_scaler()
261 pipe_ctx->stream_res.tg, in dce60_program_scaler()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c180 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
181 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths()
187 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
188 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c1201 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read()
1357 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_width_read()
1511 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_height_read()
1661 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_bits_per_pixel_read()
1806 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_width_read()
1863 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_height_read()
1935 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_chunk_size_read()
2007 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_bpg_offset_read()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c215 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h313 struct stream_resource stream_res; member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c148 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; in dce110_fill_display_configs()

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