| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_device_queue_manager_cik.c | 136 qpd->sh_mem_bases = SHARED_BASE(temp); in update_qpd_cik() 140 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_cik() 145 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in update_qpd_cik() 172 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_cik_hawaii() 175 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in update_qpd_cik_hawaii()
|
| H A D | kfd_device_queue_manager_vi.c | 176 qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT; in update_qpd_vi() 181 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_vi() 189 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in update_qpd_vi() 220 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_vi_tonga() 223 temp, qpd->sh_mem_bases); in update_qpd_vi_tonga()
|
| H A D | kfd_device_queue_manager_v10.c | 77 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); in update_qpd_v10() 79 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); in update_qpd_v10()
|
| H A D | kfd_device_queue_manager_v9.c | 73 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); in update_qpd_v9() 75 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); in update_qpd_v9()
|
| H A D | kfd_pm4_headers.h | 74 uint32_t sh_mem_bases; member 124 uint32_t sh_mem_bases; member
|
| H A D | kfd_packet_manager_vi.c | 62 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_map_process_vi()
|
| H A D | kfd_packet_manager_v9.c | 52 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_map_process_v9()
|
| H A D | kfd_pm4_headers_vi.h | 171 uint32_t sh_mem_bases; member
|
| H A D | kfd_pm4_headers_ai.h | 159 uint32_t sh_mem_bases; member
|
| H A D | kfd_priv.h | 594 uint32_t sh_mem_bases; member
|
| H A D | kfd_device_queue_manager.c | 137 qpd->sh_mem_bases); in program_sh_mem_settings()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_gfx_v9.h | 28 uint32_t sh_mem_bases);
|
| H A D | amdgpu_amdkfd_gfx_v8.c | 85 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument 94 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
|
| H A D | amdgpu_amdkfd_gfx_v7.c | 128 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument 137 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
|
| H A D | amdgpu_amdkfd_gfx_v10.c | 94 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument 101 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_program_sh_mem_settings()
|
| H A D | amdgpu_amdkfd_gfx_v9.c | 98 uint32_t sh_mem_bases) in kgd_gfx_v9_program_sh_mem_settings() argument 105 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
|
| H A D | amdgpu_amdkfd_gfx_v10_3.c | 93 uint32_t sh_mem_bases) in program_sh_mem_settings_v10_3() argument 100 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v10_3()
|
| H A D | gfx_v7_0.c | 1857 uint32_t sh_mem_bases; in gfx_v7_0_init_compute_vmid() local 1865 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v7_0_init_compute_vmid() 1876 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gfx_v7_0_init_compute_vmid()
|
| H A D | gfx_v8_0.c | 3695 uint32_t sh_mem_bases; in gfx_v8_0_init_compute_vmid() local 3703 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v8_0_init_compute_vmid() 3719 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gfx_v8_0_init_compute_vmid()
|
| H A D | gfx_v9_0.c | 2496 uint32_t sh_mem_bases; in gfx_v9_0_init_compute_vmid() local 2504 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v9_0_init_compute_vmid() 2515 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
|
| H A D | gfx_v10_0.c | 4663 uint32_t sh_mem_bases; in gfx_v10_0_init_compute_vmid() local 4671 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v10_0_init_compute_vmid() 4678 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v10_0_init_compute_vmid()
|
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/ |
| H A D | kgd_kfd_interface.h | 232 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
|