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Searched refs:sh_mem_bases (Results 1 – 22 of 22) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device_queue_manager_cik.c136 qpd->sh_mem_bases = SHARED_BASE(temp); in update_qpd_cik()
140 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_cik()
145 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in update_qpd_cik()
172 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_cik_hawaii()
175 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in update_qpd_cik_hawaii()
H A Dkfd_device_queue_manager_vi.c176 qpd->sh_mem_bases = temp << SH_MEM_BASES__SHARED_BASE__SHIFT; in update_qpd_vi()
181 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_vi()
189 qpd->pqm->process->is_32bit_user_mode, temp, qpd->sh_mem_bases); in update_qpd_vi()
220 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(temp); in update_qpd_vi_tonga()
223 temp, qpd->sh_mem_bases); in update_qpd_vi_tonga()
H A Dkfd_device_queue_manager_v10.c77 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); in update_qpd_v10()
79 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); in update_qpd_v10()
H A Dkfd_device_queue_manager_v9.c73 qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); in update_qpd_v9()
75 pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); in update_qpd_v9()
H A Dkfd_pm4_headers.h74 uint32_t sh_mem_bases; member
124 uint32_t sh_mem_bases; member
H A Dkfd_packet_manager_vi.c62 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_map_process_vi()
H A Dkfd_packet_manager_v9.c52 packet->sh_mem_bases = qpd->sh_mem_bases; in pm_map_process_v9()
H A Dkfd_pm4_headers_vi.h171 uint32_t sh_mem_bases; member
H A Dkfd_pm4_headers_ai.h159 uint32_t sh_mem_bases; member
H A Dkfd_priv.h594 uint32_t sh_mem_bases; member
H A Dkfd_device_queue_manager.c137 qpd->sh_mem_bases); in program_sh_mem_settings()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v9.h28 uint32_t sh_mem_bases);
H A Damdgpu_amdkfd_gfx_v8.c85 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument
94 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
H A Damdgpu_amdkfd_gfx_v7.c128 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument
137 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
H A Damdgpu_amdkfd_gfx_v10.c94 uint32_t sh_mem_bases) in kgd_program_sh_mem_settings() argument
101 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_program_sh_mem_settings()
H A Damdgpu_amdkfd_gfx_v9.c98 uint32_t sh_mem_bases) in kgd_gfx_v9_program_sh_mem_settings() argument
105 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
H A Damdgpu_amdkfd_gfx_v10_3.c93 uint32_t sh_mem_bases) in program_sh_mem_settings_v10_3() argument
100 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); in program_sh_mem_settings_v10_3()
H A Dgfx_v7_0.c1857 uint32_t sh_mem_bases; in gfx_v7_0_init_compute_vmid() local
1865 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v7_0_init_compute_vmid()
1876 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gfx_v7_0_init_compute_vmid()
H A Dgfx_v8_0.c3695 uint32_t sh_mem_bases; in gfx_v8_0_init_compute_vmid() local
3703 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v8_0_init_compute_vmid()
3719 WREG32(mmSH_MEM_BASES, sh_mem_bases); in gfx_v8_0_init_compute_vmid()
H A Dgfx_v9_0.c2496 uint32_t sh_mem_bases; in gfx_v9_0_init_compute_vmid() local
2504 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v9_0_init_compute_vmid()
2515 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
H A Dgfx_v10_0.c4663 uint32_t sh_mem_bases; in gfx_v10_0_init_compute_vmid() local
4671 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); in gfx_v10_0_init_compute_vmid()
4678 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v10_0_init_compute_vmid()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/
H A Dkgd_kfd_interface.h232 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);