Searched refs:reg012 (Results 1 – 13 of 13) sorted by relevance
274 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN; in init_common_regs()275 common->reg012.info_collect_en = 1; in init_common_regs()276 common->reg012.error_info_en = 0; in init_common_regs()343 if (hw_regs->common.reg012.fbc_e) in avs2d_refine_rcb_size()415 common->reg012.fbc_e = 1; in fill_registers()420 common->reg012.fbc_e = 0; in fill_registers()533 p_regs->common.reg012.scale_down_en = 0; in fill_registers()758 regs->common.reg012.scanlist_addr_valid_en = 1; in hal_avs2d_vdpu382_gen_regs()
268 common->reg012.colmv_compress_en = COLMV_COMPRESS_EN; in init_common_regs()269 common->reg012.wr_ddr_align_en = 1; in init_common_regs()270 common->reg012.info_collect_en = 1; in init_common_regs()271 common->reg012.error_info_en = 0; in init_common_regs()354 common->reg012.fbc_e = 1; in fill_registers()359 common->reg012.fbc_e = 0; in fill_registers()682 regs->common.reg012.scanlist_addr_valid_en = 1; in hal_avs2d_rkv_gen_regs()
548 common->reg012.colmv_compress_en = in set_registers()550 common->reg012.info_collect_en = 1; in set_registers()569 common->reg012.fbc_e = 1; in set_registers()574 common->reg012.fbc_e = 0; in set_registers()887 if (regs->common.reg012.fbc_e) { in h264d_refine_rcb_size()1031 regs->common.reg012.scanlist_addr_valid_en = 1; in vdpu382_h264d_gen_regs()1060 regs->common.reg012.scale_down_en = 0; in vdpu382_h264d_gen_regs()
541 common->reg012.colmv_compress_en = (pp->frame_mbs_only_flag) ? 1 : 0; in set_registers()560 common->reg012.fbc_e = 1; in set_registers()565 common->reg012.fbc_e = 0; in set_registers()678 common->reg012.wait_reset_en = 1; in init_common_regs()842 if (regs->common.reg012.fbc_e) { in h264d_refine_rcb_size()980 regs->common.reg012.scanlist_addr_valid_en = 1; in vdpu34x_h264d_gen_regs()
437 hw_reg->common.reg012.scanlist_addr_valid_en = 1; in hal_h265d_v382_output_pps_packet()533 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()542 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()748 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu382_gen_regs()753 hw_regs->common.reg012.fbc_e = 0; in hal_h265d_vdpu382_gen_regs()812 hw_regs->common.reg012.colmv_compress_en = reg_ctx->hw_info ? in hal_h265d_vdpu382_gen_regs()941 hw_regs->common.reg012.scale_down_en = 0; in hal_h265d_vdpu382_gen_regs()
433 hw_reg->common.reg012.scanlist_addr_valid_en = 1; in hal_h265d_v345_output_pps_packet()741 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()748 if (hw_regs->common.reg012.fbc_e) { in h265d_refine_rcb_size()959 hw_regs->common.reg012.fbc_e = 1; in hal_h265d_vdpu34x_gen_regs()964 hw_regs->common.reg012.fbc_e = 0; in hal_h265d_vdpu34x_gen_regs()996 hw_regs->common.reg012.wait_reset_en = 1; in hal_h265d_vdpu34x_gen_regs()1029 hw_regs->common.reg012.wr_ddr_align_en = dxva_cxt->pp.tiles_enabled_flag in hal_h265d_vdpu34x_gen_regs()1031 hw_regs->common.reg012.colmv_compress_en = 1; in hal_h265d_vdpu34x_gen_regs()
338 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()346 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()639 vp9_hw_regs->common.reg012.fbc_e = 1; in hal_vp9d_vdpu382_gen_regs()648 vp9_hw_regs->common.reg012.fbc_e = 0; in hal_vp9d_vdpu382_gen_regs()864 vp9_hw_regs->common.reg012.scale_down_en = 0; in hal_vp9d_vdpu382_gen_regs()
328 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()334 if (vp9_hw_regs->common.reg012.fbc_e) { in vp9d_refine_rcb_size()629 vp9_hw_regs->common.reg012.fbc_e = 1; in hal_vp9d_vdpu34x_gen_regs()638 vp9_hw_regs->common.reg012.fbc_e = 0; in hal_vp9d_vdpu34x_gen_regs()789 vp9_hw_regs->common.reg012.wait_reset_en = 1; in hal_vp9d_vdpu34x_gen_regs()
460 regs->reg012.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu541_prep()461 regs->reg012.pic_wfill = MPP_ALIGN(prep->width, 16) - prep->width; in setup_vepu541_prep()462 regs->reg012.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu541_prep()463 regs->reg012.pic_hfill = MPP_ALIGN(prep->height, 16) - prep->height; in setup_vepu541_prep()1303 RK_U32 pic_temp = ((regs->reg012.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in setup_vepu541_me()
257 } reg012; member
274 com->reg012.scale_down_en = 1; in vdpu382_setup_down_scale()
117 } reg012; member
122 } reg012; member