Searched refs:pmc_cntrl (Results 1 – 6 of 6) sorted by relevance
138 static struct pmc_cntrl_data pmc_cntrl[NUM_THREADS][NR_PHYS_CTRS]; variable481 pmc_cntrl[next_hdw_thread][i].evnts, in cell_virtual_cntr()482 pmc_cntrl[next_hdw_thread][i].masks); in cell_virtual_cntr()528 if (pmc_cntrl[next_hdw_thread][i].enabled) { in cell_virtual_cntr()771 pmc_cntrl[0][i].evnts = ctr[i].event; in cell_reg_setup_ppu()772 pmc_cntrl[0][i].masks = ctr[i].unit_mask; in cell_reg_setup_ppu()773 pmc_cntrl[0][i].enabled = ctr[i].enabled; in cell_reg_setup_ppu()774 pmc_cntrl[0][i].vcntr = i; in cell_reg_setup_ppu()786 pmc_cntrl[1][i].evnts = ctr[i].event + 19; in cell_reg_setup_ppu()788 pmc_cntrl[1][i].evnts = ctr[i].event; in cell_reg_setup_ppu()[all …]
18 reg = readl(&pmc->pmc_cntrl); in enable_cpu_power_rail()20 writel(reg, &pmc->pmc_cntrl); in enable_cpu_power_rail()
55 reg = readl(&pmc->pmc_cntrl); in enable_cpu_power_rail()57 writel(reg, &pmc->pmc_cntrl); in enable_cpu_power_rail()
41 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()42 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
39 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()40 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
13 uint pmc_cntrl; /* _CNTRL_0, offset 00 */ member