| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/halbb_8852b/ |
| H A D | halbb_8852b.c | 54 enum phl_phy_idx phy_idx) in halbb_stop_pmac_tx_8852b() argument
63 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
67 halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
69 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
77 enum phl_phy_idx phy_idx) in halbb_start_pmac_tx_8852b() argument
84 halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx); in halbb_start_pmac_tx_8852b()
88 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx); in halbb_start_pmac_tx_8852b()
90 halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx); in halbb_start_pmac_tx_8852b()
92 halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx); in halbb_start_pmac_tx_8852b()
103 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx); in halbb_start_pmac_tx_8852b()
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| H A D | halbb_8852b_api.h | 48 s16 pw_ofst, enum phl_phy_idx phy_idx);
50 enum phl_phy_idx phy_idx);
52 enum phl_phy_idx phy_idx);
55 enum phl_phy_idx phy_idx);
81 void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
89 void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
110 enum phl_phy_idx phy_idx);
113 enum phl_phy_idx phy_idx);
116 enum phl_phy_idx phy_idx);
137 void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
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| H A D | halbb_8852b_api.c | 30 s16 pw_ofst, enum phl_phy_idx phy_idx) in halbb_set_pwr_ul_tb_ofst_8852b() argument
39 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1); in halbb_set_pwr_ul_tb_ofst_8852b()
42 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst); in halbb_set_pwr_ul_tb_ofst_8852b()
47 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3); in halbb_set_pwr_ul_tb_ofst_8852b()
53 enum phl_phy_idx phy_idx) { in halbb_tx_triangular_shap_cfg_8852b() argument
60 enum phl_phy_idx phy_idx) { in halbb_tx_dfir_shap_cck_8852b() argument
89 halbb_set_reg_cmn(bb, 0x2300 + (i << 2), MASKDWORD, para[i], phy_idx); in halbb_tx_dfir_shap_cck_8852b()
94 void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_bb_reset_8852b() argument
104 halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx); in halbb_bb_reset_8852b()
105 halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx); in halbb_bb_reset_8852b()
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| H A D | halbb_8852b_fwofld_api.c | 30 enum phl_phy_idx phy_idx) in halbb_fwcfg_bb_phy_8852b() argument
61 BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data); in halbb_fwcfg_bb_phy_8852b()
71 void halbb_fwofld_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_fwofld_bb_reset_8852b() argument
122 void halbb_fwofld_bb_reset_all_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_fwofld_bb_reset_all_8852b() argument
127 halbb_fw_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
128 halbb_fw_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
131 halbb_fw_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
132 halbb_fw_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
134 halbb_fw_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
135 halbb_fw_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/halbb_8852b/ |
| H A D | halbb_8852b.c | 54 enum phl_phy_idx phy_idx) in halbb_stop_pmac_tx_8852b() argument
63 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
67 halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
69 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 0, phy_idx); in halbb_stop_pmac_tx_8852b()
77 enum phl_phy_idx phy_idx) in halbb_start_pmac_tx_8852b() argument
84 halbb_set_reg_cmn(bb, 0x9c4, BIT(0), 1, phy_idx); in halbb_start_pmac_tx_8852b()
88 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx); in halbb_start_pmac_tx_8852b()
90 halbb_set_reg_cmn(bb, 0x9c4, 0xffffff00, period, phy_idx); in halbb_start_pmac_tx_8852b()
92 halbb_set_reg_cmn(bb, 0x9c8, 0xffffffff, pkt_cnt, phy_idx); in halbb_start_pmac_tx_8852b()
103 halbb_set_reg_cmn(bb, 0x9c4, BIT(4), 1, phy_idx); in halbb_start_pmac_tx_8852b()
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| H A D | halbb_8852b_api.h | 48 s16 pw_ofst, enum phl_phy_idx phy_idx);
50 enum phl_phy_idx phy_idx);
52 enum phl_phy_idx phy_idx);
55 enum phl_phy_idx phy_idx);
81 void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx);
89 void halbb_bb_reset_en_8852b(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
110 enum phl_phy_idx phy_idx);
113 enum phl_phy_idx phy_idx);
116 enum phl_phy_idx phy_idx);
137 void halbb_ctrl_rx_cca_8852b(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
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| H A D | halbb_8852b_api.c | 30 s16 pw_ofst, enum phl_phy_idx phy_idx) in halbb_set_pwr_ul_tb_ofst_8852b() argument
39 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD288, BIT31, 1); in halbb_set_pwr_ul_tb_ofst_8852b()
42 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD28c, 0x1f, pw_ofst); in halbb_set_pwr_ul_tb_ofst_8852b()
47 rtw_hal_mac_write_msk_pwr_reg(bb->hal_com, (u8)phy_idx, 0xD290, 0x1f, pw_ofst - 3); in halbb_set_pwr_ul_tb_ofst_8852b()
53 enum phl_phy_idx phy_idx) { in halbb_tx_triangular_shap_cfg_8852b() argument
60 enum phl_phy_idx phy_idx) { in halbb_tx_dfir_shap_cck_8852b() argument
89 halbb_set_reg_cmn(bb, 0x2300 + (i << 2), MASKDWORD, para[i], phy_idx); in halbb_tx_dfir_shap_cck_8852b()
94 void halbb_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_bb_reset_8852b() argument
104 halbb_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx); in halbb_bb_reset_8852b()
105 halbb_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx); in halbb_bb_reset_8852b()
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| H A D | halbb_8852b_fwofld_api.c | 30 enum phl_phy_idx phy_idx) in halbb_fwcfg_bb_phy_8852b() argument
61 BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data); in halbb_fwcfg_bb_phy_8852b()
71 void halbb_fwofld_bb_reset_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_fwofld_bb_reset_8852b() argument
122 void halbb_fwofld_bb_reset_all_8852b(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_fwofld_bb_reset_all_8852b() argument
127 halbb_fw_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
128 halbb_fw_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x7, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
131 halbb_fw_set_reg_cmn(bb, 0x704, BIT(1), 1, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
132 halbb_fw_set_reg_cmn(bb, 0x704, BIT(1), 0, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
134 halbb_fw_set_reg_cmn(bb, 0x1200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
135 halbb_fw_set_reg_cmn(bb, 0x3200, BIT(28) | BIT(29) | BIT(30), 0x0, phy_idx, 0); in halbb_fwofld_bb_reset_all_8852b()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/bb/ |
| H A D | halbb_pmac_setting.c | 29 enum phl_phy_idx phy_idx) in halbb_set_pmac_tx() argument
38 halbb_set_pmac_tx_8852a(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
44 halbb_set_pmac_tx_8852a_2(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
50 halbb_set_pmac_tx_8852b(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
56 halbb_set_pmac_tx_8852c(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
64 void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_set_tmac_tx() argument
70 halbb_set_tmac_tx_8852a(bb, phy_idx); in halbb_set_tmac_tx()
76 halbb_set_tmac_tx_8852a_2(bb, phy_idx); in halbb_set_tmac_tx()
82 halbb_set_tmac_tx_8852b(bb, phy_idx); in halbb_set_tmac_tx()
88 halbb_set_tmac_tx_8852c(bb, phy_idx); in halbb_set_tmac_tx()
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| H A D | halbb_fwofld.c | 81 u32 mask, u32 val, enum phl_phy_idx phy_idx, u8 lc) in halbb_fw_set_reg_cmn() argument
87 if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1) in halbb_fw_set_reg_cmn()
96 enum phl_phy_idx phy_idx) in halbb_fwcfg_bb_phy_8852a_2() argument
124 phy_idx == HW_PHY_1) { in halbb_fwcfg_bb_phy_8852a_2()
130 phy_idx = HW_PHY_0; in halbb_fwcfg_bb_phy_8852a_2()
142 BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data); in halbb_fwcfg_bb_phy_8852a_2()
153 enum phl_phy_idx phy_idx) in halbb_fwofld_cck_en_8852a_2() argument
162 BB_DBG(bb, DBG_PHY_CONFIG, "[CCK Enable for PHY%d]\n", phy_idx); in halbb_fwofld_cck_en_8852a_2()
284 …w_set_efuse_8852a_2(struct bb_info *bb, u8 central_ch, enum rf_path path, enum phl_phy_idx phy_idx) in halbb_fw_set_efuse_8852a_2() argument
343 ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, ((tmp >> 2) & 0x1f), phy_idx, 0); in halbb_fw_set_efuse_8852a_2()
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| H A D | halbb_mp.c | 28 enum phl_phy_idx phy_idx) in halbb_mp_get_tx_ok() argument
37 tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx); in halbb_mp_get_tx_ok()
41 u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_mp_get_rx_crc_ok() argument
48 if (phy_idx == HW_PHY_0) in halbb_mp_get_rx_crc_ok()
53 ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
54 ht_ok = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_ok, cr->cnt_ht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
55 vht_ok = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_ok, cr->cnt_vht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
56 he_ok = halbb_get_reg_cmn(bb, cr->cnt_he_crc_ok, cr->cnt_he_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
69 u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_mp_get_rx_crc_err() argument
76 if (phy_idx == HW_PHY_0) in halbb_mp_get_rx_crc_err()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/bb/ |
| H A D | halbb_pmac_setting.c | 29 enum phl_phy_idx phy_idx) in halbb_set_pmac_tx() argument
38 halbb_set_pmac_tx_8852a(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
44 halbb_set_pmac_tx_8852a_2(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
50 halbb_set_pmac_tx_8852b(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
56 halbb_set_pmac_tx_8852c(bb, tx_info, phy_idx); in halbb_set_pmac_tx()
64 void halbb_set_tmac_tx(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_set_tmac_tx() argument
70 halbb_set_tmac_tx_8852a(bb, phy_idx); in halbb_set_tmac_tx()
76 halbb_set_tmac_tx_8852a_2(bb, phy_idx); in halbb_set_tmac_tx()
82 halbb_set_tmac_tx_8852b(bb, phy_idx); in halbb_set_tmac_tx()
88 halbb_set_tmac_tx_8852c(bb, phy_idx); in halbb_set_tmac_tx()
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| H A D | halbb_fwofld.c | 81 u32 mask, u32 val, enum phl_phy_idx phy_idx, u8 lc) in halbb_fw_set_reg_cmn() argument
87 if (bb->hal_com->dbcc_en && phy_idx == HW_PHY_1) in halbb_fw_set_reg_cmn()
96 enum phl_phy_idx phy_idx) in halbb_fwcfg_bb_phy_8852a_2() argument
124 phy_idx == HW_PHY_1) { in halbb_fwcfg_bb_phy_8852a_2()
130 phy_idx = HW_PHY_0; in halbb_fwcfg_bb_phy_8852a_2()
142 BB_DBG(bb, DBG_INIT, "[REG][%d]0x%04X = 0x%08X\n", phy_idx, addr, data); in halbb_fwcfg_bb_phy_8852a_2()
153 enum phl_phy_idx phy_idx) in halbb_fwofld_cck_en_8852a_2() argument
162 BB_DBG(bb, DBG_PHY_CONFIG, "[CCK Enable for PHY%d]\n", phy_idx); in halbb_fwofld_cck_en_8852a_2()
284 …w_set_efuse_8852a_2(struct bb_info *bb, u8 central_ch, enum rf_path path, enum phl_phy_idx phy_idx) in halbb_fw_set_efuse_8852a_2() argument
343 ret &= halbb_fw_set_reg_cmn(bb, 0x494c, 0xf8000000, ((tmp >> 2) & 0x1f), phy_idx, 0); in halbb_fw_set_efuse_8852a_2()
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| H A D | halbb_mp.c | 28 enum phl_phy_idx phy_idx) in halbb_mp_get_tx_ok() argument
37 tx_ok = halbb_get_reg_cmn(bb, cr->cnt_ofdmtxon, cr->cnt_ofdmtxon_m, phy_idx); in halbb_mp_get_tx_ok()
41 u32 halbb_mp_get_rx_crc_ok(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_mp_get_rx_crc_ok() argument
48 if (phy_idx == HW_PHY_0) in halbb_mp_get_rx_crc_ok()
53 ofdm_ok = halbb_get_reg_cmn(bb, cr->cnt_l_crc_ok, cr->cnt_l_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
54 ht_ok = halbb_get_reg_cmn(bb, cr->cnt_ht_crc_ok, cr->cnt_ht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
55 vht_ok = halbb_get_reg_cmn(bb, cr->cnt_vht_crc_ok, cr->cnt_vht_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
56 he_ok = halbb_get_reg_cmn(bb, cr->cnt_he_crc_ok, cr->cnt_he_crc_ok_m, phy_idx); in halbb_mp_get_rx_crc_ok()
69 u32 halbb_mp_get_rx_crc_err(struct bb_info *bb, enum phl_phy_idx phy_idx) in halbb_mp_get_rx_crc_err() argument
76 if (phy_idx == HW_PHY_0) in halbb_mp_get_rx_crc_err()
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| H A D | halbb_api_ex.h | 29 u8 halbb_wifi_event_notify(struct bb_info *bb, enum phl_msg_evt_id event, enum phl_phy_idx phy_idx);
63 void halbb_bb_reset_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
66 enum phl_phy_idx phy_idx);
69 enum phl_phy_idx phy_idx);
75 enum channel_width bw, enum phl_phy_idx phy_idx);
81 void halbb_ctrl_rx_cca(struct bb_info *bb, bool cca_en, enum phl_phy_idx phy_idx);
84 enum phl_phy_idx phy_idx);
87 enum phl_phy_idx phy_idx);
95 void halbb_pop_en(struct bb_info *bb, bool en, enum phl_phy_idx phy_idx);
97 bool halbb_querry_pop_en(struct bb_info *bb, enum phl_phy_idx phy_idx);
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/ |
| H A D | hal_api_rf.c | 52 u8 phy_idx = 0; in rtw_hal_init_rf_reg() local
54 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
55 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_a_info; in rtw_hal_init_rf_reg()
60 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
61 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_b_info; in rtw_hal_init_rf_reg()
66 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
67 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwr_byrate_info; in rtw_hal_init_rf_reg()
71 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
72 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrtrack_info; in rtw_hal_init_rf_reg()
77 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/ |
| H A D | hal_api_rf.c | 52 u8 phy_idx = 0; in rtw_hal_init_rf_reg() local
54 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
55 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_a_info; in rtw_hal_init_rf_reg()
60 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
61 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_radio_b_info; in rtw_hal_init_rf_reg()
66 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
67 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwr_byrate_info; in rtw_hal_init_rf_reg()
71 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
72 phy_reg_info = &phl_com->phy_sw_cap[phy_idx].rf_txpwrtrack_info; in rtw_hal_init_rf_reg()
77 for (phy_idx = 0; phy_idx < 1 ; phy_idx++) { in rtw_hal_init_rf_reg()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/phy/rf/ |
| H A D | halrf_ex.h | 34 enum phl_phy_idx phy_idx,
38 enum phl_phy_idx phy_idx, bool is_afe);
40 enum phl_phy_idx phy_idx,
44 enum phl_phy_idx phy_idx,
46 enum rtw_hal_status halrf_tssi_trigger(void *rf_void, enum phl_phy_idx phy_idx);
47 void halrf_do_tssi_scan(void *rf_void, enum phl_phy_idx phy_idx);
48 void halrf_tssi_enable(void *rf_void, enum phl_phy_idx phy_idx);
49 void halrf_tssi_disable(void *rf_void, enum phl_phy_idx phy_idx);
51 enum phl_phy_idx phy_idx, bool force);
53 enum phl_phy_idx phy_idx);
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| H A D | halrf_iqk.c | 20 u8 iqk_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx) in iqk_kpath() argument
23 return iqk_ops->iqk_kpath(rf, phy_idx); in iqk_kpath()
149 void iqk_macbb_setting(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_macbb_setting() argument
155 iqk_ops->iqk_macbb_setting(rf, phy_idx, path); in iqk_macbb_setting()
174 void iqk_afebb_restore(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_afebb_restore() argument
180 iqk_ops->iqk_afebb_restore(rf, phy_idx, path); in iqk_afebb_restore()
188 void iqk_get_ch_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_get_ch_info() argument
193 iqk_ops->iqk_get_ch_info(rf, phy_idx, path); in iqk_get_ch_info()
196 iqk_get_ch_info_8852a(rf, phy_idx, path); in iqk_get_ch_info()
201 bool iqk_mcc_page_sel(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_mcc_page_sel() argument
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| H A D | halrf_interface.h | 53 …pmac_pattern(rf, ppdu_type, case_id, phy_idx) rtw_hal_bb_set_plcp_pattern((rf)->hal_com, ppdu_type… argument
54 …ne halrf_set_pmac_plcp_tx(rf, plcp, usr, phy_idx, sts) rtw_hal_bb_set_plcp_tx((rf)->hal_com, plcp,… argument
55 … is_cck, cnt, period, time, phy_idx) rtw_hal_bb_set_pmac_packet_tx((rf)->hal_com, enable, is_cck, … argument
56 #define halrf_set_pmac_power(rf, dbm, phy_idx) rtw_hal_bb_set_power((rf)->hal_com, dbm, phy_idx) argument
59 #define halrf_tx_mode_switch(rf, phy_idx, mode) rtw_hal_bb_tx_mode_switch((rf)->hal_com, phy_idx, m… argument
61 #define halrf_hal_bb_backup_info(rf, phy_idx) rtw_hal_bb_backup_info((rf)->hal_com, phy_idx) argument
62 #define halrf_hal_bb_restore_info(rf, phy_idx) rtw_hal_bb_restore_info((rf)->hal_com, phy_idx) argument
100 #define halrf_bb_set_tx_pow_ref(rf, phy_idx) rtw_hal_bb_set_tx_pow_ref((rf)->hal_com, phy_idx) argument
101 #define halrf_mac_write_pwr_ofst_mode(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_mode((rf)->hal_com, p… argument
102 #define halrf_mac_write_pwr_ofst_bw(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_bw((rf)->hal_com, phy_i… argument
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| H A D | halrf.c | 30 enum phl_phy_idx phy_idx, in halrf_chl_rfk_trigger() argument
52 halrf_do_rx_gain_k(rf, phy_idx); in halrf_chl_rfk_trigger()
55 halrf_gapk_trigger(rf, phy_idx, true); in halrf_chl_rfk_trigger()
58 halrf_rx_dck_trigger(rf, phy_idx, true); in halrf_chl_rfk_trigger()
61 halrf_iqk_trigger(rf, phy_idx, force); in halrf_chl_rfk_trigger()
64 halrf_tssi_trigger(rf, phy_idx); in halrf_chl_rfk_trigger()
67 halrf_dpk_trigger(rf, phy_idx, force); in halrf_chl_rfk_trigger()
68 halrf_fw_ntfy(rf, phy_idx); in halrf_chl_rfk_trigger()
160 enum phl_phy_idx phy_idx, bool is_afe) in halrf_rx_dck_trigger() argument
181 halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_RXDCK, RFK_START); in halrf_rx_dck_trigger()
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| /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/phy/rf/ |
| H A D | halrf_ex.h | 34 enum phl_phy_idx phy_idx,
38 enum phl_phy_idx phy_idx, bool is_afe);
40 enum phl_phy_idx phy_idx,
44 enum phl_phy_idx phy_idx,
46 enum rtw_hal_status halrf_tssi_trigger(void *rf_void, enum phl_phy_idx phy_idx);
47 void halrf_do_tssi_scan(void *rf_void, enum phl_phy_idx phy_idx);
48 void halrf_tssi_enable(void *rf_void, enum phl_phy_idx phy_idx);
49 void halrf_tssi_disable(void *rf_void, enum phl_phy_idx phy_idx);
51 enum phl_phy_idx phy_idx, bool force);
53 enum phl_phy_idx phy_idx);
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| H A D | halrf_iqk.c | 20 u8 iqk_kpath(struct rf_info *rf, enum phl_phy_idx phy_idx) in iqk_kpath() argument
23 return iqk_ops->iqk_kpath(rf, phy_idx); in iqk_kpath()
149 void iqk_macbb_setting(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_macbb_setting() argument
155 iqk_ops->iqk_macbb_setting(rf, phy_idx, path); in iqk_macbb_setting()
174 void iqk_afebb_restore(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_afebb_restore() argument
180 iqk_ops->iqk_afebb_restore(rf, phy_idx, path); in iqk_afebb_restore()
188 void iqk_get_ch_info(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_get_ch_info() argument
193 iqk_ops->iqk_get_ch_info(rf, phy_idx, path); in iqk_get_ch_info()
196 iqk_get_ch_info_8852a(rf, phy_idx, path); in iqk_get_ch_info()
201 bool iqk_mcc_page_sel(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path) in iqk_mcc_page_sel() argument
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| H A D | halrf_interface.h | 53 …pmac_pattern(rf, ppdu_type, case_id, phy_idx) rtw_hal_bb_set_plcp_pattern((rf)->hal_com, ppdu_type… argument
54 …ne halrf_set_pmac_plcp_tx(rf, plcp, usr, phy_idx, sts) rtw_hal_bb_set_plcp_tx((rf)->hal_com, plcp,… argument
55 … is_cck, cnt, period, time, phy_idx) rtw_hal_bb_set_pmac_packet_tx((rf)->hal_com, enable, is_cck, … argument
56 #define halrf_set_pmac_power(rf, dbm, phy_idx) rtw_hal_bb_set_power((rf)->hal_com, dbm, phy_idx) argument
59 #define halrf_tx_mode_switch(rf, phy_idx, mode) rtw_hal_bb_tx_mode_switch((rf)->hal_com, phy_idx, m… argument
61 #define halrf_hal_bb_backup_info(rf, phy_idx) rtw_hal_bb_backup_info((rf)->hal_com, phy_idx) argument
62 #define halrf_hal_bb_restore_info(rf, phy_idx) rtw_hal_bb_restore_info((rf)->hal_com, phy_idx) argument
100 #define halrf_bb_set_tx_pow_ref(rf, phy_idx) rtw_hal_bb_set_tx_pow_ref((rf)->hal_com, phy_idx) argument
101 #define halrf_mac_write_pwr_ofst_mode(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_mode((rf)->hal_com, p… argument
102 #define halrf_mac_write_pwr_ofst_bw(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_bw((rf)->hal_com, phy_i… argument
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| H A D | halrf.c | 30 enum phl_phy_idx phy_idx, in halrf_chl_rfk_trigger() argument
52 halrf_do_rx_gain_k(rf, phy_idx); in halrf_chl_rfk_trigger()
55 halrf_gapk_trigger(rf, phy_idx, true); in halrf_chl_rfk_trigger()
58 halrf_rx_dck_trigger(rf, phy_idx, true); in halrf_chl_rfk_trigger()
61 halrf_iqk_trigger(rf, phy_idx, force); in halrf_chl_rfk_trigger()
64 halrf_tssi_trigger(rf, phy_idx); in halrf_chl_rfk_trigger()
67 halrf_dpk_trigger(rf, phy_idx, force); in halrf_chl_rfk_trigger()
68 halrf_fw_ntfy(rf, phy_idx); in halrf_chl_rfk_trigger()
160 enum phl_phy_idx phy_idx, bool is_afe) in halrf_rx_dck_trigger() argument
181 halrf_btc_rfk_ntfy(rf, (BIT(phy_idx) << 4), RF_BTC_RXDCK, RFK_START); in halrf_rx_dck_trigger()
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