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Searched refs:mmUVD_VCPU_CNTL (Results 1 – 19 of 19) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h94 #define mmUVD_VCPU_CNTL 0x3D98 macro
H A Duvd_4_2_d.h66 #define mmUVD_VCPU_CNTL 0x3d98 macro
H A Duvd_3_1_d.h68 #define mmUVD_VCPU_CNTL 0x3d98 macro
H A Duvd_5_0_d.h72 #define mmUVD_VCPU_CNTL 0x3d98 macro
H A Duvd_6_0_d.h88 #define mmUVD_VCPU_CNTL 0x3d98 macro
H A Duvd_7_0_offset.h190 #define mmUVD_VCPU_CNTL … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v3_0.c921 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
981 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
990 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v3_0_start_dpg_mode()
1070 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1148 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_start()
1152 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_start()
1504 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v3_0_stop()
1509 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v3_0_stop()
H A Dvcn_v2_5.c797 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
857 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
951 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1014 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1034 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1038 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1375 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop()
1380 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
H A Duvd_v3_1.c337 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v3_1_start()
488 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v3_1_stop()
H A Duvd_v4_2.c273 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v4_2_start()
424 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9)); in uvd_v4_2_stop()
H A Duvd_v5_0.c350 WREG32(mmUVD_VCPU_CNTL, 1 << 9); in uvd_v5_0_start()
445 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v5_0_stop()
H A Dvcn_v1_0.c853 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_start_spg_mode()
986 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
1146 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, in vcn_v1_0_stop_spg_mode()
H A Duvd_v7_0.c880 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), in uvd_v7_0_sriov_start()
1011 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, in uvd_v7_0_start()
1138 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); in uvd_v7_0_stop()
H A Dvcn_v2_0.c819 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_0_start_dpg_mode()
955 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), in vcn_v2_0_start()
1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, in vcn_v2_0_stop()
H A Duvd_v6_0.c771 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v6_0_start()
883 WREG32(mmUVD_VCPU_CNTL, 0x0); in uvd_v6_0_stop()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h376 #define mmUVD_VCPU_CNTL … macro
H A Dvcn_2_5_offset.h729 #define mmUVD_VCPU_CNTL … macro
H A Dvcn_2_0_0_offset.h658 #define mmUVD_VCPU_CNTL … macro
H A Dvcn_3_0_0_offset.h1105 #define mmUVD_VCPU_CNTL … macro