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Searched refs:mmUVD_SOFT_RESET (Results 1 – 18 of 18) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c370 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v3_1_start()
372 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v3_1_start()
374 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
391 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start()
394 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start()
491 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v3_1_stop()
H A Duvd_v4_2.c306 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start()
308 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start()
310 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
327 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
330 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
427 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v4_2_stop()
H A Duvd_v5_0.c315 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | in uvd_v5_0_start()
346 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
356 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v5_0_start()
372 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
375 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
441 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_stop()
H A Dvcn_v1_0.c856 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
863 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); in vcn_v1_0_start_spg_mode()
866 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); in vcn_v1_0_start_spg_mode()
882 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_start_spg_mode()
886 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v1_0_start_spg_mode()
1035 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); in vcn_v1_0_start_dpg_mode()
1137 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1150 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1154 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
H A Duvd_v7_0.c856 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
876 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), in uvd_v7_0_sriov_start()
905 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); in uvd_v7_0_sriov_start()
970 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1006 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, in uvd_v7_0_start()
1019 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); in uvd_v7_0_start()
1036 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), in uvd_v7_0_start()
1040 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, in uvd_v7_0_start()
1133 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, in uvd_v7_0_stop()
H A Dvcn_v2_0.c870 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
999 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
1006 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); in vcn_v2_0_start()
1009 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); in vcn_v2_0_start()
1033 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_start()
1037 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, in vcn_v2_0_start()
1173 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1178 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
1183 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v2_0_stop()
H A Dvcn_v3_0.c1081 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_start()
1084 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_start()
1513 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1515 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
1516 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); in vcn_v3_0_stop()
1518 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); in vcn_v3_0_stop()
H A Duvd_v6_0.c727 WREG32(mmUVD_SOFT_RESET, in uvd_v6_0_start()
767 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_start()
777 WREG32(mmUVD_SOFT_RESET, 0); in uvd_v6_0_start()
879 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v6_0_stop()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h83 #define mmUVD_SOFT_RESET 0x3DA0 macro
H A Duvd_4_2_d.h67 #define mmUVD_SOFT_RESET 0x3da0 macro
H A Duvd_3_1_d.h69 #define mmUVD_SOFT_RESET 0x3da0 macro
H A Duvd_5_0_d.h73 #define mmUVD_SOFT_RESET 0x3da0 macro
H A Duvd_6_0_d.h89 #define mmUVD_SOFT_RESET 0x3da0 macro
H A Duvd_7_0_offset.h192 #define mmUVD_SOFT_RESET … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h378 #define mmUVD_SOFT_RESET … macro
H A Dvcn_2_5_offset.h491 #define mmUVD_SOFT_RESET … macro
H A Dvcn_2_0_0_offset.h672 #define mmUVD_SOFT_RESET … macro
H A Dvcn_3_0_0_offset.h805 #define mmUVD_SOFT_RESET … macro