| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 52 #define mmUVD_MASTINT_EN 0x3D40 macro
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| H A D | uvd_4_2_d.h | 47 #define mmUVD_MASTINT_EN 0x3d40 macro
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| H A D | uvd_3_1_d.h | 47 #define mmUVD_MASTINT_EN 0x3d40 macro
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| H A D | uvd_5_0_d.h | 53 #define mmUVD_MASTINT_EN 0x3d40 macro
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| H A D | uvd_6_0_d.h | 69 #define mmUVD_MASTINT_EN 0x3d40 macro
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| H A D | uvd_7_0_offset.h | 152 #define mmUVD_MASTINT_EN … macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | uvd_v3_1.c | 340 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start()
405 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v3_1_start()
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| H A D | uvd_v4_2.c | 276 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
341 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
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| H A D | uvd_v5_0.c | 308 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
385 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
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| H A D | vcn_v1_0.c | 807 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v1_0_start_spg_mode()
897 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v1_0_start_spg_mode()
989 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
1043 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, in vcn_v1_0_start_dpg_mode()
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| H A D | uvd_v7_0.c | 847 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
884 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
960 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, in uvd_v7_0_start()
1051 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), in uvd_v7_0_start()
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| H A D | vcn_v2_5.c | 801 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
861 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
955 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1051 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
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| H A D | vcn_v2_0.c | 823 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
879 UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start_dpg_mode()
959 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v2_0_start()
1049 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start()
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| H A D | vcn_v3_0.c | 925 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
985 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1074 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v3_0_start()
1165 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v3_0_start()
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| H A D | uvd_v6_0.c | 806 WREG32_P(mmUVD_MASTINT_EN, in uvd_v6_0_start()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 330 #define mmUVD_MASTINT_EN … macro
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| H A D | vcn_2_5_offset.h | 533 #define mmUVD_MASTINT_EN … macro
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| H A D | vcn_2_0_0_offset.h | 538 #define mmUVD_MASTINT_EN … macro
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| H A D | vcn_3_0_0_offset.h | 863 #define mmUVD_MASTINT_EN … macro
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