Searched refs:mmSDMA0_RLC0_RB_WPTR (Results 1 – 16 of 16) sorted by relevance
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_arcturus.c | 168 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
173 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 312 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
314 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v7.c | 326 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
328 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 433 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
438 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 442 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
447 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 418 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in hqd_sdma_load_v10_3()
423 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in hqd_sdma_load_v10_3()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 300 #define mmSDMA0_RLC0_RB_WPTR … macro
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| H A D | sdma0_4_0_offset.h | 388 #define mmSDMA0_RLC0_RB_WPTR 0x0145 macro
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| H A D | sdma0_4_2_offset.h | 384 #define mmSDMA0_RLC0_RB_WPTR … macro
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| H A D | sdma0_4_2_2_offset.h | 388 #define mmSDMA0_RLC0_RB_WPTR … macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 218 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| H A D | oss_3_0_1_d.h | 257 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| H A D | oss_2_0_d.h | 272 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| H A D | oss_3_0_d.h | 379 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 380 #define mmSDMA0_RLC0_RB_WPTR … macro
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| H A D | gc_10_3_0_offset.h | 376 #define mmSDMA0_RLC0_RB_WPTR … macro
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