Searched refs:mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI (Results 1 – 14 of 14) sorted by relevance
262 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI … macro
266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 macro
266 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI … macro
193 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 macro
220 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 macro
252 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 macro
345 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x3486 macro
718 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], in sdma_v3_0_gfx_resume()
620 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), in sdma_v5_2_gfx_resume()
690 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), in sdma_v5_0_gfx_resume()
1197 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI, in sdma_v4_0_gfx_resume()
259 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI … macro
246 #define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI … macro