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Searched refs:mmSDMA0_GFX_RB_WPTR_HI (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h216 #define mmSDMA0_GFX_RB_WPTR_HI … macro
H A Dsdma0_4_0_offset.h220 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
H A Dsdma0_4_2_offset.h216 #define mmSDMA0_GFX_RB_WPTR_HI … macro
H A Dsdma0_4_2_2_offset.h220 #define mmSDMA0_GFX_RB_WPTR_HI … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c281 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_2_ring_get_wptr()
326 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_2_ring_set_wptr()
614 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_2_gfx_resume()
648 … WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); in sdma_v5_2_gfx_resume()
H A Dsdma_v5_0.c332 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr()
377 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), in sdma_v5_0_ring_set_wptr()
684 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); in sdma_v5_0_gfx_resume()
718 … WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); in sdma_v5_0_gfx_resume()
H A Dsdma_v4_0.c720 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); in sdma_v4_0_ring_get_wptr()
767 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, in sdma_v4_0_ring_set_wptr()
1158 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0); in sdma_v4_0_gfx_resume()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h214 #define mmSDMA0_GFX_RB_WPTR_HI … macro
H A Dgc_10_3_0_offset.h200 #define mmSDMA0_GFX_RB_WPTR_HI … macro