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Searched refs:mmRLC_CGCG_CGLS_CTRL (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c81 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
212 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
242 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
H A Dsi.c536 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
635 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
733 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
813 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
893 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
H A Dgfx_v8_0.c205 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
303 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
317 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
348 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
380 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
422 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
466 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
480 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
567 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
577 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
[all …]
H A Dgfx_v7_0.c3530 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3531 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); in gfx_v7_0_rlc_resume()
3585 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
3606 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v7_0_enable_cgcg()
3618 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v7_0_enable_cgcg()
H A Dgfx_v9_0.c3098 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_0_rlc_resume()
4972 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
4984 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
4993 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
4998 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
5176 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v9_0_get_clockgating_state()
H A Dgfx_v10_0.c4984 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v10_0_rlc_resume()
7469 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
7476 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
7485 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
7490 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
7665 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v10_0_get_clockgating_state()
H A Dgfx_v6_0.c2566 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v6_0_enable_cgcg()
2597 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v6_0_enable_cgcg()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h1133 #define mmRLC_CGCG_CGLS_CTRL 0x3101 macro
H A Dgfx_7_0_d.h1281 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
H A Dgfx_7_2_d.h1294 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
H A Dgfx_8_1_d.h1394 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
H A Dgfx_8_0_d.h1392 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6045 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_2_1_offset.h6243 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_1_offset.h6267 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_10_1_0_offset.h9365 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_10_3_0_offset.h9189 #define mmRLC_CGCG_CGLS_CTRL … macro