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Searched refs:mmIH_RB_CNTL_RING2 (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dnavi10_ih.c77 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in force_update_wptr_for_self_int()
80 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in force_update_wptr_for_self_int()
125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in navi10_ih_enable_interrupts()
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in navi10_ih_enable_interrupts()
190 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in navi10_ih_disable_interrupts()
200 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in navi10_ih_disable_interrupts()
383 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in navi10_ih_irq_init()
393 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in navi10_ih_irq_init()
488 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in navi10_ih_get_wptr()
H A Dvega10_ih.c80 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_enable_interrupts()
90 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in vega10_ih_enable_interrupts()
145 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_disable_interrupts()
155 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in vega10_ih_disable_interrupts()
312 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_irq_init()
322 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in vega10_ih_irq_init()
417 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_get_wptr()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Dosssys_4_0_offset.h148 #define mmIH_RB_CNTL_RING2 … macro
H A Dosssys_4_0_1_offset.h148 #define mmIH_RB_CNTL_RING2 … macro
H A Dosssys_5_0_0_offset.h148 #define mmIH_RB_CNTL_RING2 … macro