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Searched refs:mmIH_RB_CNTL_RING1 (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dnavi10_ih.c67 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in force_update_wptr_for_self_int()
76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
109 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_enable_interrupts()
119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_enable_interrupts()
170 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_disable_interrupts()
180 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_disable_interrupts()
354 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_irq_init()
367 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_irq_init()
486 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_get_wptr()
H A Dvega10_ih.c64 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_enable_interrupts()
74 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_enable_interrupts()
125 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_disable_interrupts()
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_disable_interrupts()
282 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_irq_init()
295 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_irq_init()
415 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_get_wptr()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Dosssys_4_0_offset.h136 #define mmIH_RB_CNTL_RING1 … macro
H A Dosssys_4_0_1_offset.h136 #define mmIH_RB_CNTL_RING1 … macro
H A Dosssys_5_0_0_offset.h136 #define mmIH_RB_CNTL_RING1 … macro