Searched refs:mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR (Results 1 – 4 of 4) sorted by relevance
120 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
281 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 macro
756 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, in goya_late_init()917 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()919 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_qman()960 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()962 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_dma_ch()1185 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, in goya_init_cpu_queues()1650 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1652 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_qman()1699 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()1701 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR); in goya_init_mme_cmdq()[all …]
812 WREG32(mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR, GAUDI_EVENT_INTS_REGISTER); in gaudi_late_init()1902 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_pci_dma_qman()1905 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_pci_dma_qman()1942 lower_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_dma_core()1944 upper_32_bits(CFG_BASE + mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_dma_core()2059 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_hbm_dma_qman()2062 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_hbm_dma_qman()2177 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_mme_qman()2180 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_mme_qman()2298 mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR)); in gaudi_init_tpc_qman()[all …]