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Searched refs:mmCP_RB_WPTR_POLL_CNTL (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c80 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
211 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
H A Dsi.c534 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
633 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
731 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
811 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
891 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
H A Dgfx_v9_0.c2855 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); in gfx_v9_0_init_gfx_power_gating()
2858 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); in gfx_v9_0_init_gfx_power_gating()
4933 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_3d_clock_gating()
4937 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_3d_clock_gating()
4987 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_coarse_grain_clock_gating()
4991 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
H A Dgfx_v8_0.c302 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
465 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
566 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
672 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
H A Dgfx_v7_0.c3917 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3920 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v7_0_init_gfx_cgpg()
H A Dgfx_v10_0.c7434 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_3d_clock_gating()
7438 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_3d_clock_gating()
7479 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_coarse_grain_clock_gating()
7483 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h524 #define mmCP_RB_WPTR_POLL_CNTL 0x21C2 macro
H A Dgfx_7_0_d.h513 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
H A Dgfx_7_2_d.h526 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
H A Dgfx_8_1_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
H A Dgfx_8_0_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h217 #define mmCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_9_2_1_offset.h211 #define mmCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_9_1_offset.h217 #define mmCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_10_1_0_offset.h2219 #define mmCP_RB_WPTR_POLL_CNTL … macro
H A Dgc_10_3_0_offset.h2300 #define mmCP_RB_WPTR_POLL_CNTL … macro