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Searched refs:mmCP_MEC1_F32_INT_DIS (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_1_d.h286 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
H A Dgfx_8_0_d.h285 #define mmCP_MEC1_F32_INT_DIS 0x30bd macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800),
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2611 #define mmCP_MEC1_F32_INT_DIS macro
H A Dgc_9_2_1_offset.h2815 #define mmCP_MEC1_F32_INT_DIS macro
H A Dgc_9_1_offset.h2881 #define mmCP_MEC1_F32_INT_DIS macro
H A Dgc_10_1_0_offset.h4941 #define mmCP_MEC1_F32_INT_DIS macro
H A Dgc_10_3_0_offset.h4592 #define mmCP_MEC1_F32_INT_DIS macro