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Searched refs:mmCP_HQD_PQ_WPTR_POLL_ADDR_HI (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/pm/inc/
H A Dpolaris10_pwrvirus.h1510 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
1520 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
1530 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
1540 { 0x000000b4, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI },
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v10.c284 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_hqd_load()
H A Damdgpu_amdkfd_gfx_v9.c295 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in kgd_gfx_v9_hqd_load()
H A Damdgpu_amdkfd_gfx_v10_3.c269 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), in hqd_load_v10_3()
H A Dmes_v10_1.c769 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in mes_v10_1_queue_init_register()
H A Dgfx_v9_0.c3633 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v9_0_kiq_init_register()
H A Dgfx_v10_0.c6587 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in gfx_v10_0_kiq_init_register()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h581 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
H A Dgfx_7_2_d.h594 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
H A Dgfx_8_1_d.h644 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
H A Dgfx_8_0_d.h644 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2847 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI … macro
H A Dgc_9_2_1_offset.h3031 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI … macro
H A Dgc_9_1_offset.h3075 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI … macro
H A Dgc_10_1_0_offset.h5311 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI … macro
H A Dgc_10_3_0_offset.h4944 #define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI … macro