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Searched refs:hw_core (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/common/
H A Dmali_pp.c52 …if (_MALI_OSK_ERR_OK == mali_hw_core_create(&core->hw_core, resource, MALI200_REG_SIZEOF_REGISTER_… in mali_pp_create()
80 …ERROR(("Mali PP: Failed to setup interrupt handlers for PP core %s\n", core->hw_core.description)); in mali_pp_create()
84 MALI_PRINT_ERROR(("Mali PP: Failed to add core %s to group\n", core->hw_core.description)); in mali_pp_create()
87 mali_hw_core_delete(&core->hw_core); in mali_pp_create()
105 mali_hw_core_delete(&core->hw_core); in mali_pp_delete()
131 …mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_… in mali_pp_stop_bus()
145 …if (mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS) & MALI200_REG_VAL_STA… in mali_pp_stop_bus_wait()
150 … to stop bus on %s. Status: 0x%08x\n", core->hw_core.description, mali_hw_core_register_read(&core… in mali_pp_stop_bus_wait()
212 MALI_DEBUG_PRINT(2, ("Mali PP: Hard reset of core %s\n", core->hw_core.description)); in mali_pp_hard_reset()
215 …mali_hw_core_register_write_relaxed(&core->hw_core, reset_wait_target_register, reset_invalid_valu… in mali_pp_hard_reset()
[all …]
H A Dmali_gp.c37 …if (_MALI_OSK_ERR_OK == mali_hw_core_create(&core->hw_core, resource, MALIGP2_REGISTER_ADDRESS_SPA… in mali_gp_create()
59 …ERROR(("Mali GP: Failed to setup interrupt handlers for GP core %s\n", core->hw_core.description)); in mali_gp_create()
63 MALI_PRINT_ERROR(("Mali GP: Failed to add core %s to group\n", core->hw_core.description)); in mali_gp_create()
66 mali_hw_core_delete(&core->hw_core); in mali_gp_create()
82 mali_hw_core_delete(&core->hw_core); in mali_gp_delete()
91 …mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_CMD, MALIGP2_REG_VAL_CMD_STOP_BU… in mali_gp_stop_bus()
105 …if (mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_STATUS) & MALIGP2_REG_VAL_STA… in mali_gp_stop_bus_wait()
111 MALI_PRINT_ERROR(("Mali GP: Failed to stop bus on %s\n", core->hw_core.description)); in mali_gp_stop_bus_wait()
126 MALI_DEBUG_PRINT(4, ("Mali GP: Hard reset of core %s\n", core->hw_core.description)); in mali_gp_hard_reset()
128 mali_hw_core_register_write(&core->hw_core, reset_wait_target_register, reset_invalid_value); in mali_gp_hard_reset()
[all …]
H A Dmali_mmu.c114 if (_MALI_OSK_ERR_OK == mali_hw_core_create(&mmu->hw_core, resource, MALI_MMU_REGISTERS_SIZE)) { in mali_mmu_create()
133 …MALI_PRINT_ERROR(("Mali MMU: Failed to setup interrupt handlers for MMU %s\n", mmu->hw_core.descri… in mali_mmu_create()
138 MALI_PRINT_ERROR(("Mali MMU: Failed to add core %s to group\n", mmu->hw_core.description)); in mali_mmu_create()
140 mali_hw_core_delete(&mmu->hw_core); in mali_mmu_create()
157 mali_hw_core_delete(&mmu->hw_core); in mali_mmu_delete()
165 …mali_hw_core_register_write(&mmu->hw_core, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ENABLE_PAGI… in mali_mmu_enable_paging()
168 …if (mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS) & MALI_MMU_STATUS_BIT_PAGI… in mali_mmu_enable_paging()
173 …equest failed, MMU status is 0x%08X\n", mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTE… in mali_mmu_enable_paging()
185 u32 mmu_status = mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS); in mali_mmu_enable_stall()
197 …mali_hw_core_register_write(&mmu->hw_core, MALI_MMU_REGISTER_COMMAND, MALI_MMU_COMMAND_ENABLE_STAL… in mali_mmu_enable_stall()
[all …]
H A Dmali_pmu.c40 if (_MALI_OSK_ERR_OK == mali_hw_core_create(&pmu->hw_core, in mali_pmu_create()
64 mali_hw_core_delete(&pmu->hw_core); in mali_pmu_delete()
79 mali_hw_core_register_write_relaxed(&pmu->hw_core, in mali_pmu_reset()
81 mali_hw_core_register_write_relaxed(&pmu->hw_core, in mali_pmu_reset()
97 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_up_all()
114 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_down_all()
129 MALI_DEBUG_ASSERT(0 == (mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_down()
137 stat = mali_hw_core_register_read(&pmu->hw_core, in mali_pmu_power_down()
150 mali_hw_core_register_write(&pmu->hw_core, in mali_pmu_power_down()
164 mali_hw_core_register_write(&pmu->hw_core, in mali_pmu_power_down()
[all …]
H A Dmali_l2_cache.c129 if (_MALI_OSK_ERR_OK != mali_hw_core_create(&cache->hw_core, in mali_l2_cache_create()
136 cache_size = mali_hw_core_register_read(&cache->hw_core, in mali_l2_cache_create()
150 cache->hw_core.description)); in mali_l2_cache_create()
151 mali_hw_core_delete(&cache->hw_core); in mali_l2_cache_create()
194 mali_hw_core_delete(&cache->hw_core); in mali_l2_cache_delete()
234 &cache->hw_core, in mali_l2_cache_power_down()
236 mali_hw_core_register_write(&cache->hw_core, in mali_l2_cache_power_down()
242 &cache->hw_core, in mali_l2_cache_power_down()
244 mali_hw_core_register_write(&cache->hw_core, in mali_l2_cache_power_down()
289 mali_hw_core_register_write(&cache->hw_core, in mali_l2_cache_core_set_counter_src()
[all …]
H A Dmali_dlbu.c77 struct mali_hw_core hw_core; /**< Common for all HW cores */ member
115 if (_MALI_OSK_ERR_OK == mali_hw_core_create(&core->hw_core, resource, MALI_DLBU_SIZE)) { in mali_dlbu_create()
120 MALI_PRINT_ERROR(("Failed to reset DLBU %s\n", core->hw_core.description)); in mali_dlbu_create()
121 mali_hw_core_delete(&core->hw_core); in mali_dlbu_create()
135 mali_hw_core_delete(&dlbu->hw_core); in mali_dlbu_delete()
145 MALI_DEBUG_PRINT(4, ("Mali DLBU: mali_dlbu_reset: %s\n", dlbu->hw_core.description)); in mali_dlbu_reset()
156 …mali_hw_core_register_write_array_relaxed(&dlbu->hw_core, MALI_DLBU_REGISTER_MASTER_TLLIST_PHYS_AD… in mali_dlbu_reset()
167 …mali_hw_core_register_write(&dlbu->hw_core, MALI_DLBU_REGISTER_PP_ENABLE_MASK, dlbu->pp_cores_mask… in mali_dlbu_update_mask()
211 …mali_hw_core_register_write_array_relaxed(&dlbu->hw_core, MALI_DLBU_REGISTER_TLLIST_VBASEADDR, reg… in mali_dlbu_config_job()
H A Dmali_pp.h27 struct mali_hw_core hw_core; /**< Common for all HW cores */ member
84 return core->hw_core.description; in mali_pp_core_description()
89 u32 rawstat_used = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT) & in mali_pp_get_interrupt_result()
103 return mali_hw_core_register_read(&core->hw_core, in mali_pp_get_rawstat()
110 u32 status = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_STATUS); in mali_pp_is_active()
116 …mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MA… in mali_pp_mask_all_interrupts()
121 …mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MA… in mali_pp_enable_interrupts()
128 mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, addr); in mali_pp_write_addr_renderer_list()
135 mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_STACK, addr); in mali_pp_write_addr_stack()
H A Dmali_gp.h26 struct mali_hw_core hw_core; /**< Common for all HW cores */ member
58 return core->hw_core.description; in mali_gp_core_description()
63 u32 stat_used = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_STAT) & in mali_gp_get_interrupt_result()
85 return mali_hw_core_register_read(&core->hw_core, in mali_gp_get_rawstat()
91 u32 status = mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_STATUS); in mali_gp_is_active()
97 …mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MA… in mali_gp_mask_all_interrupts()
117 mali_hw_core_register_write(&core->hw_core, in mali_gp_enable_interrupts()
124 return mali_hw_core_register_read(&core->hw_core, MALIGP2_REG_ADDR_MGMT_PLBU_ALLOC_START_ADDR); in mali_gp_read_plbu_alloc_start_addr()
H A Dmali_mmu.h66 struct mali_hw_core hw_core; /**< Common for all HW cores */ member
90 u32 rawstat_used = mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_INT_RAWSTAT); in mali_mmu_get_interrupt_result()
101 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_INT_STATUS); in mali_mmu_get_int_status()
106 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_INT_RAWSTAT); in mali_mmu_get_rawstat()
111 mali_hw_core_register_write(&mmu->hw_core, MALI_MMU_REGISTER_INT_MASK, 0); in mali_mmu_mask_all_interrupts()
116 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_STATUS); in mali_mmu_get_status()
121 return mali_hw_core_register_read(&mmu->hw_core, MALI_MMU_REGISTER_PAGE_FAULT_ADDR); in mali_mmu_get_page_fault_addr()
H A Dmali_broadcast.c20 struct mali_hw_core hw_core; member
38 if (_MALI_OSK_ERR_OK == mali_hw_core_create(&bcast_unit->hw_core, in mali_bcast_unit_create()
56 mali_hw_core_delete(&bcast_unit->hw_core); in mali_bcast_unit_delete()
117 mali_hw_core_register_write(&bcast_unit->hw_core, in mali_bcast_reset()
122 mali_hw_core_register_write(&bcast_unit->hw_core, in mali_bcast_reset()
134 mali_hw_core_register_write(&bcast_unit->hw_core, in mali_bcast_disable()
139 mali_hw_core_register_write(&bcast_unit->hw_core, in mali_bcast_disable()
H A Dmali_group.c532 MALI_PRINT(("Dump Group %s\n", group->gp_core->hw_core.description));
535 …0x%04x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i, mali_hw_core_register_read(&group->gp_core->hw_core, i),
536 mali_hw_core_register_read(&group->gp_core->hw_core, i + 4),
537 mali_hw_core_register_read(&group->gp_core->hw_core, i + 8),
538 mali_hw_core_register_read(&group->gp_core->hw_core, i + 12)));
543 MALI_PRINT(("Dump Group %s\n", group->pp_core->hw_core.description));
546 …0x%04x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i, mali_hw_core_register_read(&group->pp_core->hw_core, i),
547 mali_hw_core_register_read(&group->pp_core->hw_core, i + 4),
548 mali_hw_core_register_read(&group->pp_core->hw_core, i + 8),
549 mali_hw_core_register_read(&group->pp_core->hw_core, i + 12)));
[all …]
H A Dmali_pmu.h26 struct mali_hw_core hw_core; member
99 u32 stat = mali_hw_core_register_read(&pmu->hw_core, PMU_REG_ADDR_MGMT_STATUS); in mali_pmu_get_mask()
H A Dmali_l2_cache.h28 struct mali_hw_core hw_core; member
H A Dmali_executor.c815 group->mmu->hw_core.description)); in mali_executor_interrupt_mmu()
2644 MALI_PRINT(("\tPP #%d: %s\n", group->pp_core->core_id, group->pp_core->hw_core.description)); in mali_executor_running_status_print()
2649 MALI_PRINT(("\tPP #%d: %s\n", group->pp_core->core_id, group->pp_core->hw_core.description)); in mali_executor_running_status_print()
2654 MALI_PRINT(("\tPP #%d: %s\n", group->pp_core->core_id, group->pp_core->hw_core.description)); in mali_executor_running_status_print()
2665 …MALI_PRINT(("\tchild group(%s) running job: %p\n", group->pp_core->hw_core.description, group->pp_… in mali_executor_running_status_print()
2666 …MALI_PRINT(("\tchild group(%s)->status: %d\n", group->pp_core->hw_core.description, group->state)); in mali_executor_running_status_print()
2667 …MALI_PRINT(("\tchild group(%s) SW power: %s\n", group->pp_core->hw_core.description, group->power_… in mali_executor_running_status_print()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/mali400/mali/linux/
H A Dmali_kernel_sysfs.c154 struct mali_hw_core *hw_core; in hw_core_base_addr_read() local
156 hw_core = (struct mali_hw_core *)filp->private_data; in hw_core_base_addr_read()
157 MALI_DEBUG_ASSERT_POINTER(hw_core); in hw_core_base_addr_read()
159 r = snprintf(buffer, 64, "0x%lX\n", hw_core->phys_addr); in hw_core_base_addr_read()
1232 …debugfs_create_file("base_addr", 0400, mali_gp_gpx_dir, &gp_core->hw_core, &hw_core_base_addr_fops… in mali_sysfs_register()
1261 …debugfs_create_file("base_addr", 0400, mali_pp_ppx_dir, &pp_core->hw_core, &hw_core_base_addr_fops… in mali_sysfs_register()
1294 …debugfs_create_file("base_addr", 0400, mali_l2_l2x_dir, &l2_cache->hw_core, &hw_core_base_addr_fop… in mali_sysfs_register()