Searched refs:enc_rsl (Results 1 – 6 of 6) sorted by relevance
1364 pic_cime_temp = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 64; in vepu540_h265_set_me_ram()1373 tile_ctu_endx = ((regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 - 1; in vepu540_h265_set_me_ram()1586 regs->enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1; in hal_h265e_v541_gen_regs()1587 regs->enc_rsl.pic_wfill = (syn->pp.pic_width & 0x7) in hal_h265e_v541_gen_regs()1589 regs->enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1; in hal_h265e_v541_gen_regs()1590 regs->enc_rsl.pic_hfill = (syn->pp.pic_height & 0x7) in hal_h265e_v541_gen_regs()
137 } enc_rsl; member
454 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu540c_prep()456 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu540c_prep()1222 RK_S32 pic_wdt_align = ((base_regs->enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64 * 2; in calc_cime_parameter()
383 } enc_rsl; member
699 regs->reg_base.enc_rsl.pic_wd8_m1 = MPP_ALIGN(prep->width, 16) / 8 - 1; in setup_vepu580_prep()701 regs->reg_base.enc_rsl.pic_hd8_m1 = MPP_ALIGN(prep->height, 16) / 8 - 1; in setup_vepu580_prep()
361 } enc_rsl; member