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Searched refs:cw1 (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/board/freescale/common/
H A Dics307_clk.c101 static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2) in ics307_clk_freq() argument
104 unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1); in ics307_clk_freq()
127 debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2, in ics307_clk_freq()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn30.c85 const struct dmub_window *cw1) in dmub_dcn30_backdoor_load() argument
105 dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
109 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn30_backdoor_load()
111 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, in dmub_dcn30_backdoor_load()
H A Ddmub_dcn20.c144 const struct dmub_window *cw1) in dmub_dcn20_backdoor_load() argument
164 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn20_backdoor_load()
168 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); in dmub_dcn20_backdoor_load()
170 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, in dmub_dcn20_backdoor_load()
H A Ddmub_srv.c388 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
403 cw1.offset.quad_part = stack_fb->gpu_addr; in dmub_srv_hw_init()
404 cw1.region.base = DMUB_CW1_BASE; in dmub_srv_hw_init()
405 cw1.region.top = cw1.region.base + stack_fb->size - 1; in dmub_srv_hw_init()
415 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); in dmub_srv_hw_init()
H A Ddmub_dcn30.h39 const struct dmub_window *cw1);
H A Ddmub_dcn20.h167 const struct dmub_window *cw1);
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h243 const struct dmub_window *cw1);