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Searched refs:_2u (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/common/
H A Dvepu5xx_common.c28 ._2u = {.r_coeff = -38, .g_coeff = -74, .b_coeff = 112, .offset = 128},
35 ._2u = {.r_coeff = -26, .g_coeff = -87, .b_coeff = 112, .offset = 128},
46 ._2u = {.r_coeff = -43, .g_coeff = -85, .b_coeff = 128, .offset = 128},
53 ._2u = {.r_coeff = -29, .g_coeff = -99, .b_coeff = 128, .offset = 128},
H A Dvepu5xx_common.h38 VepuRgb2YuvCoeffs _2u; member
/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c495 regs->reg019.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu541_prep()
496 regs->reg019.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu541_prep()
497 regs->reg019.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu541_prep()
504 regs->reg021.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu541_prep()
H A Dhal_h264e_vepu580.c754 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu580_prep()
755 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu580_prep()
756 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu580_prep()
763 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu580_prep()
/OK3568_Linux_fs/external/mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c1144 regs->src_udfu.wght_r2u = cfg_coeffs->_2u.r_coeff; in vepu541_h265_set_pp_regs()
1145 regs->src_udfu.wght_g2u = cfg_coeffs->_2u.g_coeff; in vepu541_h265_set_pp_regs()
1146 regs->src_udfu.wght_b2u = cfg_coeffs->_2u.b_coeff; in vepu541_h265_set_pp_regs()
1153 regs->src_udfo.ofst_u = cfg_coeffs->_2u.offset; in vepu541_h265_set_pp_regs()
H A Dhal_h265e_vepu580.c1954 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu580_h265_set_pp_regs()
1955 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu580_h265_set_pp_regs()
1956 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu580_h265_set_pp_regs()
1963 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu580_h265_set_pp_regs()