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Searched refs:VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h9481 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L macro
H A Ddce_8_0_sh_mask.h11011 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 macro
H A Ddce_10_0_sh_mask.h11395 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 macro
H A Ddce_11_0_sh_mask.h11207 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 macro
H A Ddce_11_2_sh_mask.h12461 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x1000000 macro
H A Ddce_12_0_sh_mask.h2070 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h1620 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK … macro
H A Ddcn_2_1_0_sh_mask.h121 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h120 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK … macro
H A Ddcn_3_0_0_sh_mask.h100 #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK … macro