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Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c472 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_disable_clock_gating()
597 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_enable_clock_gating()
599 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_enable_clock_gating()
658 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
660 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_5.c562 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_disable_clock_gating()
668 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
670 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
727 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_enable_clock_gating()
729 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_enable_clock_gating()
H A Dvcn_v2_0.c498 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_disable_clock_gating()
600 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
602 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
659 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_enable_clock_gating()
661 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_enable_clock_gating()
H A Dvcn_v3_0.c659 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_disable_clock_gating()
787 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
789 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
843 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_enable_clock_gating()
845 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_enable_clock_gating()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h418 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Duvd_3_1_sh_mask.h222 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
H A Duvd_4_0_sh_mask.h37 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000 macro
H A Duvd_4_2_sh_mask.h222 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h242 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
H A Duvd_6_0_sh_mask.h244 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h911 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_2_5_sh_mask.h1979 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h1929 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h2709 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT … macro