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Searched refs:UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT (Results 1 – 16 of 16) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h419 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT macro
H A Duvd_3_1_sh_mask.h224 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
H A Duvd_4_0_sh_mask.h33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 macro
H A Duvd_4_2_sh_mask.h224 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
H A Duvd_5_0_sh_mask.h246 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
H A Duvd_6_0_sh_mask.h248 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c476 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_disable_clock_gating()
600 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_enable_clock_gating()
661 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_5.c565 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_5_disable_clock_gating()
671 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
730 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_5_enable_clock_gating()
H A Dvcn_v2_0.c501 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_0_disable_clock_gating()
603 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
662 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_0_enable_clock_gating()
H A Duvd_v3_1.c212 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | in uvd_v3_1_set_dcm()
H A Duvd_v4_2.c610 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) | in uvd_v4_2_set_dcm()
H A Dvcn_v3_0.c662 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v3_0_disable_clock_gating()
790 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
846 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v3_0_enable_clock_gating()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h912 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT macro
H A Dvcn_2_5_sh_mask.h1980 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT macro
H A Dvcn_2_0_0_sh_mask.h1930 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT macro
H A Dvcn_3_0_0_sh_mask.h2710 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT macro