Searched refs:SDMA_PKT_POLL_REGMEM_DW5_INTERVAL (Results 1 – 9 of 9) sorted by relevance
| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v2_4.c | 295 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_hdp_flush()
785 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_pipeline_sync()
811 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_vm_flush()
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| H A D | sdma_v3_0.c | 469 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_hdp_flush()
1056 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_pipeline_sync()
1082 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_vm_flush()
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| H A D | sdma_v5_2.c | 403 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_hdp_flush()
1106 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_pipeline_sync()
1145 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_2_ring_emit_reg_wait()
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| H A D | sdma_v5_0.c | 469 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_hdp_flush()
1169 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_pipeline_sync()
1208 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_0_ring_emit_reg_wait()
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| H A D | tonga_sdma_pkt_open.h | 2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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| H A D | iceland_sdma_pkt_open.h | 2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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| H A D | vega10_sdma_pkt_open.h | 2511 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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| H A D | sdma_v4_0.c | 887 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_0_wait_reg_mem()
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| H A D | navi10_sdma_pkt_open.h | 3835 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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