Searched refs:REG_DSI_28nm_PHY_PLL_VCOLPF_CFG (Results 1 – 2 of 2) sorted by relevance
229 pll_write(base + REG_DSI_28nm_PHY_PLL_VCOLPF_CFG, 0x31); in dsi_pll_28nm_clk_set_rate()
1147 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c macro