Searched refs:REG_DSI_28nm_PHY_PLL_SDM_CFG4 (Results 1 – 2 of 2) sorted by relevance
221 pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00); in dsi_pll_28nm_clk_set_rate()
1213 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048 macro