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Searched refs:REG_DDR3_MR2_CWL_MASK (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_hws_hw_training_def.h253 #define REG_DDR3_MR2_CWL_MASK 0x7 macro
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h279 #define REG_DDR3_MR2_CWL_MASK 0x7 macro
H A Dddr3_dfs.c483 & ~(REG_DDR3_MR2_CWL_MASK << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_high_2_low()
1181 ~(REG_DDR3_MR2_CWL_MASK << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
H A Dddr3_hw_training.c145 reg &= REG_DDR3_MR2_CWL_MASK; in ddr3_hw_training()