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Searched refs:REG_DDR3_MR0_CL_MASK (Results 1 – 3 of 3) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_hws_hw_training_def.h227 #define REG_DDR3_MR0_CL_MASK 0x74 macro
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h255 #define REG_DDR3_MR0_CL_MASK 0x74 macro
H A Dddr3_dfs.c473 ~REG_DDR3_MR0_CL_MASK; in ddr3_dfs_high_2_low()
1168 ~REG_DDR3_MR0_CL_MASK; in ddr3_dfs_low_2_high()